MDAC Capacitor-Switch Layout for Smaller Pipeline ADC Area
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Solution Overview
Problem
Conventional pipeline analog-to-digital converters (ADCs) have a large number of switches in their multiplying digital-to-analog converters (MDACs), which occupy a significant area in the circuit due to each sampling capacitor being coupled to one sampling switch and one decoding switch, leading to increased size and power consumption.
Innovation Solution
The MDAC structure is modified to include at least two sampling capacitor sets coupled in parallel, with each set connected to a sampling switch and decoding switch, allowing for shared switches and reducing the total number of switches, thereby decreasing the occupied area. This structure includes a sub digital-to-analog converter decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit, where the capacitor-switch circuit comprises multiple sampling capacitor sets that are summed to produce an analog signal corresponding to a digital quantity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each sampling capacitor is coupled to one sampling switch and one decoding switch in conventional MDAC, then the circuit achieves proper sampling and decoding functions, but the number of switches increases significantly, occupying large circuit area
Solution Approach 1:
The patent merges multiple sampling capacitors into parallel sets, where each set shares a common sampling switch and decoding switch. Specifically, multiple sampling capacitors (e.g., Cs1, Cs2, Cs3, Cs4) are grouped into parallel sets, with each set controlled by shared switches rather than individual switches per capacitor. This combining approach maintains the necessary sampling and decoding functions while reducing the total switch count from 14 switches (7 sampling + 7 decoding) to fewer switches, thereby reducing circuit area occupation.
2Area of stationary object
If the number of switches is reduced by sharing switches among sampling capacitor sets, then the circuit area decreases, but the complexity of switch control and timing may increase
Solution Approach 1:
The patent segments the sampling capacitors into distinct parallel sets (e.g., first sampling capacitor set, second sampling capacitor set, third sampling capacitor set, fourth sampling capacitor set), where each set can be controlled independently by its own shared sampling and decoding switches. This segmentation allows for modular control timing, where each set can be activated or deactivated based on specific decoding results, simplifying the overall control logic compared to managing individual switches for each capacitor.
Solution Approach 2:
The shared sampling switches and decoding switches serve multiple functions: they control multiple sampling capacitors within their respective sets, enable parallel operation of multiple capacitor sets, and can be selectively activated based on decoding results. This multi-functionality reduces the total switch count while maintaining the ability to perform precise sampling and decoding operations across all capacitor sets.
Data Source
AI summary
A multiplying digital-to-analog converter (MDAC) is provided. The MDAC includes a sub DAC decoding circuit, a capacitor-switch circuit, and an operation amplifier circuit. The capacitor-switch circuit includes at least two sampling capacitor sets which are coupled in parallel. The number of sampling capacitors in one of the sampling capacitor sets is larger than or equal to two. Each sampling capacitor set is coupled to an analog-signal input quantity through a sampling switch and to a corresponding output terminal of the sub DAC decoding circuit through a decoding switch. The sub DAC decoding circuit decodes a digital quantity and outputs a corresponding analog signal at each output terminal, such that the corresponding analog signals are applied to the respective sampling capacitor sets through the decoding switches and summed by the respective sampling capacitor sets to obtain an analog-signal quantity corresponding to the digital quantity.