MDAC Input Switch Topology for Low-Voltage High-Speed Sampling

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Solution Overview

Problem

Designing a high-speed analog-to-digital converter (ADC) that operates under low supply voltage is challenging due to the emergence of a dead-zone in switches, which prevents correct sampling of input signals by the capacitor block.

Innovation Solution

A multiplying digital-to-analog converter (MDAC) design that uses a differential operational amplifier with PMOS switches for the input switch block, setting the common mode voltage equal to the supply voltage, and employing PMOS and NMOS transistors in switches to minimize impedance and capacitance, ensuring effective sampling and reducing dead-zones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the common mode voltage is set to VDD/2 for low supply voltage operation, then power consumption is reduced, but a dead-zone emerges in the switch preventing correct sampling

Engineering Contradiction:

Improvepower consumptionVSAvoidsampling accuracy

Core Design Contradiction:

Use of energy by stationary objectVSReliability

Solution Approach 1:

The patent changes the common mode voltage parameter from the conventional VDD/2 to a new value that eliminates the dead-zone while maintaining low power consumption. This parameter change resolves the contradiction by finding an optimal operating point that satisfies both power efficiency and sampling accuracy requirements.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by stationary object

If the common mode voltage is set to VDD/2, then the operational amplifier can operate at low supply voltage, but the input stage becomes difficult to design for high speed operation

Engineering Contradiction:

Improvesupply voltageVSAvoidoperating speed

Core Design Contradiction:

Use of energy by stationary objectVSSpeed

Solution Approach 1:

The patent modifies the common mode voltage parameter to enable high-speed operation at low supply voltage. By adjusting this critical parameter, the input stage can be designed to operate efficiently at both low voltage and high speed, resolving the trade-off between power consumption and operating speed.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If NMOS and PMOS transistors are combined in switches, then switching performance is improved, but a dead-zone appears when supply voltage is low

Engineering Contradiction:

Improveswitching performanceVSAvoidsampling accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the common mode voltage parameter to eliminate the dead-zone that appears in NMOS-PMOS combined switches at low supply voltage. This parameter adjustment maintains the advantages of combined transistor switches while resolving the sampling accuracy issue.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8031097B2Multiplying digital-to-analog converter for high speed and low supply voltage

Publication Date: 2011.10.04 MEDIATEK INC

AI summary

A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.