MDAC Capacitor Switching Circuit Without Extra Clock Phases
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Solution Overview
Problem
Existing multiplying digital-to-analog converters (MDACs) in pipeline analog-to-digital converters (ADCs) face implementation difficulties due to the requirement of multiple clocks, which hinders circuit speed and design simplicity.
Innovation Solution
The proposed MDAC incorporates a capacitor switching amplifier circuit with a selection circuit, sampling and amplifying circuits, and an operational amplifier, which allows for the reduction of clock requirements by implementing a correlated level shifting technique that eliminates the need for an estimation phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the correlated level shifting (CLS) technique is applied to the MDAC of a pipeline ADC, then the required gain of the operational amplifier is decreased, but the number of clocks increases and circuit speed decreases
Solution Approach 1:
The patent applies preliminary action by performing level shifting during the sampling phase before the amplification phase. The capacitor switching amplifier circuit performs correlated level shifting on the input signal during sampling, so that the operational amplifier only needs to amplify the differential signal without handling large common-mode voltage swings. This eliminates the need for additional clocks while maintaining the power consumption benefits of CLS.
2Power
If the correlated level shifting (CLS) technique is applied to the MDAC of a pipeline ADC, then the required gain of the operational amplifier is decreased, but the implementation difficulty increases
Solution Approach 1:
The patent merges the level shifting function with the sampling and amplification functions into a single capacitor switching amplifier circuit. The same capacitor network that performs sampling also performs correlated level shifting, eliminating the need for separate level shifting circuitry and additional clocks. This integration simplifies the overall implementation while maintaining the power consumption advantages.
Solution Approach 2:
The capacitor switching amplifier circuit performs multiple functions simultaneously: sampling the input signal, performing correlated level shifting, and preparing the signal for amplification. This multi-functional approach eliminates the need for dedicated level shifting circuitry and additional control clocks, reducing implementation complexity.
3Power
If the correlated level shifting (CLS) technique is applied to the MDAC of a pipeline ADC, then the required gain of the operational amplifier is decreased, but the area of the operational amplifier increases
Solution Approach 1:
By performing level shifting during the sampling phase before amplification, the operational amplifier only needs to handle small differential signals rather than large voltage swings. This preliminary level shifting allows the use of a smaller, lower-power operational amplifier with reduced area requirements while maintaining the power consumption benefits of the CLS technique.
Data Source
AI summary
A multiplying digital-to-analog converter (MDAC) has two input terminals and two output terminals and includes: an analog-to-digital converter (ADC), a selection circuit, first and second sampling and amplifying circuits, an operational amplifier, and an amplification and level shifting circuit. The ADC generates a selection signal according to first and second input signals. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to one of the two reference voltages. The second sampling and amplifying circuit samples and amplifies the second input signal according to the other reference voltage. The operational amplifier has first and second output nodes. The amplification and level shifting circuit amplifies the first and second input signals and level shifts voltages at the first and second output nodes.