Multiplying Digital-to-Analog Converter With Unity Feedback Factor
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Solution Overview
Problem
Existing multiplying digital-to-analog converters (MDACs) in pipeline ADCs have insufficient feedback factors, leading to significant circuit area and power consumption, making them uncompetitive.
Innovation Solution
The proposed MDAC incorporates a switched capacitor (SC) circuit with a feedback factor of 1, reducing the number of sampling capacitors from four to two, thereby decreasing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MDAC designs with feedback factors of 0.5 or 0.25 are used, then the circuit can operate with standard operational amplifiers, but the area and power consumption of the operational amplifiers become quite considerable
Solution Approach 1:
The patent changes the feedback factor parameter from conventional values (0.5 or 0.25) to 1. This parameter change fundamentally alters the operational amplifier requirements, allowing the use of smaller, more power-efficient amplifiers while maintaining circuit functionality. The feedback factor change is achieved through specific capacitor configuration in the switched capacitor circuit.
Solution Approach 2:
The patent applies different capacitor values strategically in the feedback path versus input path. By making the feedback capacitor equal to the input capacitor (Cb=Ca), the local quality of the feedback network is optimized to achieve unity feedback factor, while other capacitors are sized differently to maintain signal integrity and minimize operational amplifier burden.
2Ease of operation
If the capacitance value of capacitors in sampling and amplifying circuits is increased, then the capacitors can be driven more easily by reference voltages, but the overall power consumption increases
Solution Approach 1:
The patent optimizes capacitor value parameters to achieve the right balance. Rather than using uniformly large capacitance values, the design uses specific ratios (Cb=Ca for feedback, with other capacitors sized according to signal requirements) that provide sufficient driving capability while minimizing total capacitance and associated power consumption.
3Area of stationary object
If the feedback factor is increased to 1, then the area and power consumption of the operational amplifier are reduced, but the circuit design becomes more complex
Solution Approach 1:
The patent segments the circuit into distinct functional blocks with clear capacitor assignments. The switched capacitor circuit is divided into input sampling capacitors, feedback capacitors, and hold capacitors, each with specific value relationships. This segmentation makes the unity feedback factor design more manageable by distributing the complexity across well-defined components rather than requiring a monolithic complex circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the area and power consumption of the operational amplifier, enhancing the competitiveness of the MDAC while maintaining equivalent performance to existing 1.5-bit and 2.5-bit MDACs.
Implementation Method 1
The sampling and amplifying circuits 130p and 130n each include two capacitors (including the capacitor C1a or the capacitor C1b) and six switches
Implementation Method 2
The sampling and amplifying circuit 130p (sampling and amplifying circuit 130n) samples the input signal Vsp (input signal Vsn) in the sampling phase and amplifies the signal component dV of the input signal Vsp (input signal Vsn) in the amplifying phase
Data Source
AI summary
A multiplying digital-to-analog converter (MDAC) includes an analog-to-digital converter (ADC), a selection circuit, an operational amplifier, a first switched capacitor (SC) circuit, a second SC circuit, a first switch, a second switch, a first load capacitor, and a second load capacitor. The ADC generates a selection signal according to a first input signal and a second input signal. The selection circuit generates a first reference voltage and a second reference voltage according to the selection signal. The first and second SC circuits amplify the signal component of the first and second input signals. The first switch receives the second reference voltage. The second switch receives the first reference voltage. The first load capacitor receives the second reference voltage through the first switch. The second load capacitor receives the first reference voltage through the second switch.