Configurable Co-Processor for MDCT Audio Compression
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Solution Overview
Problem
Conventional audio compression systems face inefficiencies in performing repetitive tasks such as MDCT and inverse MDCT operations, particularly in terms of power consumption and computational efficiency, as they rely on hardware and software loops that are not optimized for low power and high efficiency.
Innovation Solution
A configurable co-processor system that performs MDCT or inverse MDCT operations by pre-modulating data, performing an intermediate transform, and post-modulating the data, with configuration bits determining the signs and magnitudes of matrix coefficients and addressing modes to optimize matrix multiplication and data access, thereby reducing power consumption and processing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional hardware and software loops are used to perform MDCT and inverse MDCT operations, then the system can perform the required audio compression and decompression functions, but power consumption increases and computational efficiency decreases
Solution Approach 1:
The patent replaces conventional software-based loop structures with dedicated hardware circuitry specifically designed to perform MDCT and inverse MDCT operations. This hardware implementation includes specialized functional units for pre-modulation, intermediate transform, and post-modulation that operate in parallel rather than sequentially, thereby reducing power consumption while significantly improving computational efficiency for audio compression and decompression tasks
Solution Approach 2:
The patent divides the MDCT and inverse MDCT operations into distinct modular functional units: pre-modulation units, intermediate transform units, and post-modulation units. Each unit is independently implemented in hardware and can operate concurrently, eliminating the sequential overhead of software loops and improving both power efficiency and computational throughput
2Speed
If conventional software loops are used for repetitive tasks, then the system maintains flexibility in handling different operations, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent substitutes software loop execution with dedicated hardware circuits that perform repetitive MDCT and inverse MDCT operations. The hardware functional units are designed to execute pre-modulation, intermediate transform, and post-modulation operations in parallel, achieving higher processing speeds while consuming less power compared to sequential software processing
Solution Approach 2:
The patent implements pipelined hardware architecture where pre-modulation, intermediate transform, and post-modulation units operate continuously and concurrently. Data flows through the pipeline without interruption, eliminating the start-stop nature of software loops and maintaining continuous useful action that improves processing speed while reducing power consumption through efficient resource utilization
Data Source
AI summary
In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.