Message Digest Hardware Accelerator Varying Bit Widths
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Solution Overview
Problem
Existing hash function systems struggle to efficiently process hash functions of varying bit widths, particularly requiring significant redesign for 64-bit implementations, which is not fully utilized in many devices still using 32-bit architectures.
Innovation Solution
A message digest hardware accelerator (MDHA) using multiple banks of narrow-bit-width registers allows for computation of hash functions in multiple bit widths by processing carry bits between sets of 32-bit registers, enabling wider bit width features without significant redesign of legacy systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 64-bit hash algorithms (SHA-384, SHA-512) are implemented, then hash computation capability for large-block data is improved, but device complexity and redesign requirements increase significantly
Solution Approach 1:
The patent divides the hash computation into two separate 32-bit paths (even and odd paths) that operate in parallel. Each path uses standard 32-bit registers and logic, avoiding the need for 64-bit hardware. The even path processes bytes at positions 0, 2, 4, 6... while the odd path processes bytes at positions 1, 3, 5, 7..., effectively segmenting the 64-bit computation into manageable 32-bit segments that can be handled by existing architecture.
Solution Approach 2:
The patent merges the results of two independent 32-bit hash computations to produce the final 64-bit hash output. The even path computes hash(EVEN) from even-positioned bytes and the odd path computes hash(ODD) from odd-positioned bytes. These two 32-bit results are then combined through concatenation or arithmetic operations to form the complete 64-bit hash value, allowing the system to support both 32-bit and 64-bit algorithms using the same hardware.
2Productivity
If 64-bit hash paths are implemented, then processing capability for video and large-block data is improved, but resource utilization in 32-bit devices decreases
Solution Approach 1:
The patent creates a universal hash computation system that can handle both 32-bit and 64-bit algorithms using the same hardware infrastructure. By implementing two parallel 32-bit paths that can be selectively activated or combined, the system achieves multi-functionality - it can process small messages using standard 32-bit algorithms efficiently, and process large video blocks using 64-bit algorithms by combining the two paths, thereby eliminating unused capacity and maximizing resource utilization across different workloads.
3Adaptability or versatility
If multiple bit width hash algorithms are supported, then system versatility is improved, but register and logic design complexity increases
Solution Approach 1:
The patent implements a dynamic configuration system where the hash computation mode can be switched between 32-bit and 64-bit algorithms at runtime. The control logic dynamically selects which path (even or odd) to activate and how to combine their results based on the required algorithm. This dynamic approach allows the same static hardware to adapt to different bit width requirements without requiring separate dedicated registers or logic for each algorithm type, thereby reducing overall design complexity while maintaining versatility.
Data Source
AI summary
A technique for producing a hashed output of an input message according to any number of hash algorithms (e.g. SHA-256, SHA-348, SHA-512) having varying bit widths is described. At least a portion of the input message is stored in a first group of registers each having a bit width equal to a first bit width (e.g. 32 bits). If the selected hash algorithm has a larger bit width (e.g. 64 bits), a remainder of the input message is stored in a second plurality of registers each having a bit width equal to the first bit width. The hashed output is then computed according to the selected hash algorithm.