MDIO Bus Bulk Data Transfer Using Clause 45 Address Frames
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Solution Overview
Problem
The existing MDIO interface specified in IEEE Std 802.3-2015 is inefficient for bulk data transfer due to the need for multiple frames in indirect write transactions, which results in slow data transfer rates.
Innovation Solution
Implementing a method that uses a single address frame followed by multiple write frames to transfer bulk data, with the follower device performing a post-write-increment-address action, reducing the number of frames required and enhancing transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If indirect write transactions are used to transfer bulk data over MDIO bus, then data transfer can be performed using standard Clause 45 frames, but the number of frames required increases to 2×N frames for N blocks of data, resulting in slow transfer rate
Solution Approach 1:
The patent segments the bulk data transfer process into two distinct phases: (1) a single address frame that specifies the target register address and follower device, and (2) multiple consecutive write frames that transfer N blocks of data. This segmentation allows the address to be set once and reused for multiple data blocks, eliminating the need to repeat the address frame for each block, thereby reducing total frames from 2×N to N+1 frames.
Solution Approach 2:
The patent performs the address setting action in advance by transmitting a single address frame before the bulk data transfer. This preliminary action establishes the target register address in the follower device's address register, allowing subsequent write frames to directly write data to the specified address without needing to carry address information. This preliminary address setup enables efficient bulk transfer of N data blocks using only N write frames afterward.
2Productivity
If conventional indirect write transactions are used, then each data block requires a separate address frame and write frame, but this results in doubled frame count and reduced transfer efficiency
Solution Approach 1:
The patent merges the address specification function into a single preliminary address frame that serves all N data blocks. Instead of pairing each address frame with its corresponding write frame (as in conventional indirect write), the invention combines the address setup phase with multiple data write phases, allowing one address frame to support N write frames. This merging reduces the total frame count from 2×N to N+1 frames.
Solution Approach 2:
The address frame in the patent serves a universal function by specifying the target register address that will be used for multiple subsequent write operations. The address register in the follower device is designed to store and reuse this address information across N different write frames, making the address specification multi-functional rather than single-use. This universality allows the same address to be applied to N different data blocks without repeating the address frame.
3Reliability
If address frames are transmitted for every data block in indirect write transactions, then data can be written to target registers, but the transfer process becomes slow due to the repeated address frame transmissions
Solution Approach 1:
The patent performs the address frame transmission as a preliminary action before the bulk data transfer. The single address frame is transmitted once to set the target register address in the follower device's address register. This preliminary address setup ensures data writing accuracy is maintained while eliminating the need to repeat address frame transmissions for each of the N data blocks, thereby saving significant time.
Solution Approach 2:
The follower device's address register automatically stores and reuses the address information from the single address frame for all subsequent write frames. This self-service mechanism allows the follower device to maintain the target address without requiring repeated address frames from the leader device, ensuring reliable data writing while reducing communication overhead and transmission time.
Data Source
AI summary
Methods for transfer of bulk data from a leader device to a follower device over a bus are described. The methods employ address frames and write frames. The bus, the address frames, and the write frames are compatible with Clause 45 of IEEE Std 802.3-2015. The methods achieve a reduction in the number of frames employed to transfer data as contrasted with conventional indirect write transactions. After transmitting on a Management Data Input/Output (MDIO) data signal an address frame that specifies the follower device and that contains the address of an initial register, the leader device proceeds to transmit on the MDIO data signal multiple write frames that specify the target follower device, the multiple write frames transmitted one at a time, each write frame containing a different block of the bulk data. A follower device implements a post-write-increment-address action, despite the absence of any definition in Clause 45 of IEEE Std 802.3-2015 of a post-write-increment-address frame.