MDLL Aperture Circuit With Phase Interpolation for Low Jitter
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Solution Overview
Problem
Existing multiplying delay-locked loop (MDLL) circuits face issues with high-frequency applications due to gate delays in selection control logic, which cause phase errors and fixed-pattern jitter, limiting their operation beyond 2 GHz, and require careful design to reduce cycle-to-cycle jitter.
Innovation Solution
Incorporating a phase interpolator (PI) that phase mixes internal signals to provide a correction signal to the selection control logic, allowing for synchronized injection of edges and decoupling the timing of the selection signal from the reference and output signals, thereby reducing cycle-to-cycle jitter and enabling higher frequency operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate delays in selection control logic are reduced to enable high-frequency operation, then operating frequency can be increased, but phase errors and fixed-pattern jitter increase
Solution Approach 1:
The patent applies preliminary action by generating the selection signal earlier and adjusting its phase in advance to compensate for the gate delays in the selection control logic. The phase interpolator pre-adjusts the selection signal phase based on measured or estimated delays, so that when the signal passes through the logic gates, the cumulative delay results in the correct timing alignment, thereby reducing phase errors at high frequencies.
Solution Approach 2:
The patent implements feedback by measuring the actual phase error and fixed-pattern jitter resulting from gate delays, then using this information to adjust the phase interpolator settings. The system continuously monitors the timing alignment between reference and output signals and dynamically adjusts the selection signal phase to minimize errors, enabling stable high-frequency operation.
2Manufacturing precision
If selection control logic timing is tightly coupled to reference and output signals to minimize jitter, then cycle-to-cycle jitter is reduced, but the system becomes more sensitive to process, voltage, and temperature variations
Solution Approach 1:
The patent applies dynamics by making the selection control logic timing flexible and adjustable rather than fixed. The phase interpolator dynamically adjusts the phase of the selection signal based on operating conditions, allowing the system to adapt to process, voltage, and temperature variations. This dynamic adjustment decouples the timing from rigid signal edges while maintaining low jitter through controlled phase shifting.
Solution Approach 2:
The patent changes the phase parameter of the selection signal to optimize performance under different conditions. By varying the phase of the selection signal through the phase interpolator, the system can maintain proper timing alignment despite PVT variations, reducing both jitter and sensitivity to environmental changes.
3Manufacturing precision
If phase comparator design and selection circuit timing are carefully optimized to reduce fixed-pattern jitter, then jitter performance improves, but device complexity increases
Solution Approach 1:
The patent introduces a phase interpolator as an intermediary component between the selection control logic and the multiplexer. This intermediary device simplifies the overall selection circuit design by providing a dedicated mechanism for phase adjustment, rather than requiring complex timing optimization throughout the entire selection path. The phase interpolator acts as a buffer that absorbs timing variations and provides clean, adjustable phase signals.
Data Source
AI summary
A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.