MDLL Clock Generation with Edge Injection for Low Jitter
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Solution Overview
Problem
Integrated circuits face challenges in generating clock signals with reduced jitter, particularly when processing high-frequency digital and RF signals, as existing methods fail to effectively prevent noise-induced jitter, which degrades high-speed operations.
Innovation Solution
A clock generation apparatus and method utilizing a phase detector, voltage generator, switch, clock generator, and divider to create a multiplying delay locked loop (MDLL) circuit that injects reference clock edges into the output clock signal, separating edge injection for locking and feedback, and switching between constant and variable voltages to minimize jitter during coarse and fine tuning periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a higher frequency clock signal is utilized to process high-speed digital and RF signals, then the processing speed of the integrated circuit is improved, but clock jitter is generated which degrades the high-speed operation
Solution Approach 1:
The patent segments the clock generation process into distinct phases: a coarse tuning period for initial frequency acquisition and a fine tuning period for jitter reduction. During coarse tuning, the delay cells are adjusted to achieve the target frequency, and during fine tuning, the reference clock edges are injected to reduce jitter without disrupting the frequency setting. This segmentation allows each phase to optimize for its specific goal without compromising the other.
Solution Approach 2:
The patent applies preliminary action by first establishing the correct frequency through coarse tuning before initiating the fine tuning process. The coarse tuning period prepares the system by setting the delay cells to the appropriate values, ensuring that when fine tuning begins, the clock signal is already at the correct frequency and only needs jitter reduction. This preliminary frequency establishment prevents disruption during the jitter reduction phase.
Solution Approach 3:
The patent implements periodic action through the multiplying delay locked loop (MDLL) architecture, where reference clock edges are periodically injected into the output clock signal at multiple points around the loop. This periodic injection occurs at specific phases determined by the fine tuning control signal, creating multiple injection points that collectively reduce jitter throughout the clock cycle without requiring continuous disruption of the clock signal.
2Reliability
If reference clock edges are injected into the output clock signal to reduce jitter, then clock jitter is reduced, but the loop locking may be disrupted
Solution Approach 1:
The patent segments the operation into coarse tuning and fine tuning periods, with the reference clock edge injection occurring only during fine tuning when the loop is already locked. This temporal segmentation prevents injection-related disruptions during the critical frequency acquisition phase while still providing jitter reduction benefits during the stable fine tuning phase.
Solution Approach 2:
The patent performs preliminary frequency acquisition and loop locking through coarse tuning before initiating reference clock edge injection. By ensuring the loop is already locked and the frequency is correctly established, the subsequent injection process operates on a stable foundation, minimizing the risk of disrupting the locking condition while still achieving jitter reduction.
Solution Approach 3:
The patent applies local quality by injecting reference clock edges at specific localized points in the loop rather than uniformly throughout. The fine tuning control signal determines specific injection phases and locations, allowing jitter reduction to be applied selectively at critical points in the clock signal path without broadly affecting the entire loop's stability. This localized approach preserves loop locking while achieving jitter reduction.
3Device complexity
If noise effects are not prevented in the clock generation process, then the circuit operation is simplified, but jitter is generated which degrades high-speed operation
Solution Approach 1:
The patent introduces an intermediary mechanism—the multiplying delay locked loop with controlled reference clock edge injection—that mediates between the simple delay cell architecture and the requirement for low jitter. This intermediary structure adds controlled complexity through the phase detector, voltage generator, switch, and fine tuning control signal, but these components work together to filter and reduce noise effects while maintaining the fundamental simplicity of the delay cell-based frequency multiplication approach.
Data Source
Figure 1
Figure 2A
Figure 2B~3
AI summary
A clock generation apparatus includes a pulse generator (420) configured to generate a pulse signal (PUL) and a selection signal (SEL) using a reference clock signal (CK_R), a delay line circuit (440; 440a; 440b), a switch (300) and a controller (500). The delay line circuit (440; 440a; 440b) selects, as an input signal to a delay path, the pulse signal (PUL) or a fed back portion of a delay clock signal (CK_DL) at an output of the delay path, where the selection is based on the selection signal (SEL); and thereby generates the delay clock signal (CK_DL). The switch (300) switches a first voltage (V1) or a second voltage (V2) to the delay line circuit (440; 440a; 440b) for its operation, where the first voltage (V1) further provides power to the pulse generator (420). The second voltage (V2) is generated based on a phase difference between the reference clock signal (CK_R) and the delay clock signal (CK_DL). The controller (500) generates a switch control signal (C_SW) based on a frequency of the delay clock signal (CK_DL).