MDLL Delay-Line Calibration for Fine Clock Synchronization
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Solution Overview
Problem
Existing multiplying-delay-locked-loops (MDLLs) face limitations in delay control granularity, leading to synchronization discrepancies between upconverted clock cycles and reference clock cycles, especially with large scaling factors, as they adjust delay by a coarse increment of 2*N*Δt per clock cycle, which is insufficient for precise reconciliation.
Innovation Solution
The proposed solution involves independently adjusting cycle times of subsets of upconverted clock cycles by varying the delay in the delay line at different rates, using a tap selector and counter to generate a tap select control word that dynamically reconfigures the delay line, allowing for finer adjustments based on phase detection errors, thereby reducing synchronization discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the delay line adjusts delay by a coarse increment of 2*N*Δt per clock cycle, then the control system is simpler to implement, but the synchronization precision between upconverted clock cycles and reference clock cycles deteriorates
Solution Approach 1:
The patent segments the delay adjustment process into two independent components: a coarse adjustment component that operates once per reference clock cycle, and a fine adjustment component that operates on a per-upconverted-clock-cycle basis. This segmentation allows the system to achieve fine synchronization precision without requiring the entire control system to operate at fine granularity, thus maintaining reasonable complexity.
Solution Approach 2:
The patent introduces dynamic adjustment capability where the delay line can be reconfigured at different rates for different subsets of upconverted clock cycles. The system dynamically selects between coarse and fine adjustment modes based on the specific synchronization needs of each clock cycle, enabling adaptive precision control.
2Device complexity
If the delay line is reconfigured once per reference clock cycle, then the device complexity is reduced, but the ability to reconcile multiple upconverted clock cycles with the reference clock cycle deteriorates
Solution Approach 1:
The patent divides the upconverted clock cycles into multiple subsets, each potentially requiring different delay adjustments. By segmenting the clock cycles and allowing independent delay control for each subset, the system can reliably reconcile multiple upconverted cycles with the reference cycle without requiring full reconfiguration of all cycles simultaneously.
Solution Approach 2:
The patent applies local quality by allowing different delay adjustment strategies for different subsets of clock cycles within the same reference clock period. This enables targeted optimization for specific synchronization issues while maintaining overall system stability, improving reconciliation reliability without uniform complexity increase.
3Ease of operation
If the delay adjustment increment is increased to reduce control complexity, then the ease of operation improves, but the manufacturing precision of clock cycle alignment deteriorates
Solution Approach 1:
The patent implements dynamic adjustment granularity where the system can switch between coarse adjustment (easier operation, lower precision) and fine adjustment (harder operation, higher precision) based on the specific alignment needs. This dynamic approach allows the system to maintain ease of operation for routine adjustments while achieving high precision when needed.
Solution Approach 2:
The patent introduces an intermediary control mechanism that bridges the gap between coarse control signals and fine alignment requirements. The intermediary layer processes the control adjustments and applies appropriate granularity levels, making the overall system easier to operate while maintaining high alignment precision through the intermediary's fine-tuning capability.
Data Source
AI summary
Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle.