MDLL Ring Oscillator Jitter Compensation for Wideband Phase Noise
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Solution Overview
Problem
Wireless communication devices face challenges with phase noise and jitter, which impair their performance in radio frequency operations, necessitating effective methods for compensation to enhance communication quality.
Innovation Solution
The implementation of a multiplying delay lock loop (MDLL) circuitry with a ring oscillator and jitter estimation and compensation mechanisms, utilizing stochastic time to digital converters (STDCs) to determine and adjust for jitter, thereby improving phase noise suppression across a wider bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase noise suppression methods are used, then phase noise is suppressed within a limited bandwidth, but the bandwidth coverage is insufficient for higher data-rate protocols
Solution Approach 1:
The patent segments the phase noise suppression function into multiple parallel paths: a narrowband suppression path for low-offset frequencies and a wideband suppression path for high-offset frequencies. Each path processes specific frequency ranges independently, allowing the system to achieve both narrowband performance and wideband coverage simultaneously.
Solution Approach 2:
The patent extends the suppression capability from a single-dimensional narrowband approach to a two-dimensional frequency coverage by introducing parallel suppression paths that operate at different frequency offsets. This dimensional expansion allows comprehensive phase noise suppression across the entire required bandwidth.
2Adaptability or versatility
If the suppression bandwidth is extended to meet higher data-rate protocols, then adaptability improves, but system complexity increases
Solution Approach 1:
The complex wideband suppression task is segmented into manageable narrowband sub-tasks handled by parallel suppression paths. Each path uses simpler processing suitable for its specific frequency range, reducing the complexity burden on individual components while achieving overall wideband suppression.
Solution Approach 2:
The patent merges multiple parallel suppression paths with different frequency coverage characteristics into a unified wideband suppression system. The outputs of individual simpler paths are combined to achieve the overall complex wideband suppression function, distributing complexity across multiple manageable units.
Data Source
AI summary
Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.