MDLL Pulse Filtering for Input Jitter Tolerance

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Solution Overview

Problem

Conventional multiplying delay locked loops (MDLLs) lack input jitter filtering, leading to issues with CPU clock cycle times becoming too short due to high input jitter, particularly affecting CPU performance in audio applications.

Innovation Solution

Incorporating a pulse filter into the MDLL circuit to selectively skip clock cycles with early reference edges, thereby eliminating negative period jitter and ensuring stable CPU cycle times even with high input jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional MDLL is used without input jitter filtering, then the device complexity is reduced and power consumption is lower, but the CPU clock cycle time becomes too short due to high input jitter causing negative period jitter

Engineering Contradiction:

ImproveCPU clock cycle time stabilityVSAvoidMDLL circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A pulse filter is introduced as an intermediary component between the MDLL and the CPU clock output. The pulse filter selectively removes early reference edges that cause negative period jitter, while allowing normal clock cycles to pass through. This mediator protects the CPU from jitter-induced timing errors without requiring fundamental changes to the MDLL architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution segments the clock signal processing into distinct functional blocks: the MDLL generates the multiplied clock signal, the pulse filter processes and conditions the signal by removing harmful jitter components, and the output stage delivers the cleaned clock to the CPU. This segmentation allows each block to be optimized independently while maintaining overall system simplicity.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If high input jitter is tolerated without filtering, then the ease of operation is improved by avoiding clean master-clock requirements, but the CPU period jitter increases causing timing margin violations at higher CPU clock frequencies

Engineering Contradiction:

ImproveInput clock toleranceVSAvoidCPU clock cycle time precision

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The pulse filter converts the harmful effect of early reference edges (which cause negative period jitter) into a beneficial filtering action. By detecting and removing these early edges, the system transforms the jitter problem into an opportunity to improve CPU clock stability. The filter uses the presence of early edges as a trigger to selectively block them, turning a harmful input characteristic into a controlled filtering mechanism.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12483250B2Multiplying delay locked loop with high tolerance to input jitter

Publication Date: 2025.11.25 ANALOG DEVICES INT UNLTD CO

AI summary

In an aspect, a clock generation system includes a pulse filter configured to receive an input reference clock signal and a multiplied input reference clock signal and filter the multiplied input reference clock signal to generate an output reference clock signal with reduced negative period jitter with respect to the input reference clock signal by selectively skipping clock cycles of the multiplied input reference clock signal corresponding to input reference clock signal edges.