MDLL Realignment Error Compensation for Spectral Purity
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Solution Overview
Problem
Multiplying delay locked loops (MDLLs) face realignment errors due to periodic injection of reference clock signals, which degrade the spectral purity of output clock signals, impacting the performance of electronic systems relying on timing control.
Innovation Solution
Incorporating a multiplexed oscillator with a control circuit and an integrate and subtract circuit, which selectively injects a reference clock signal and compensates for realignment errors by determining the difference between integrals of the oscillator signal over injected and natural periods, thereby reducing or eliminating realignment errors without the need for additional calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock signal is periodically injected into the oscillator to provide phase realignment, then timing accuracy is improved, but realignment error is introduced that degrades spectral purity
Solution Approach 1:
The patent implements a feedback mechanism where the integrate and subtract circuit continuously monitors the oscillator signal and generates a compensation signal based on the realignment error. This compensation signal is fed back to adjust the oscillator, eliminating the harmful realignment error while maintaining the timing accuracy benefits of periodic reference injection
Solution Approach 2:
The patent converts the harmful realignment error into a useful compensation signal. By integrating the oscillator signal and subtracting it from a reference, the system generates an error signal that is then used to adjust the oscillator, transforming the previously harmful realignment error into a beneficial correction mechanism that improves spectral purity
2Object-generated harmful factors
If traditional phase-frequency detectors and charge pumps are used to correct realignment error, then spectral purity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for complex phase-frequency detectors and charge pumps by using a simplified integrate and subtract circuit. This extraction of unnecessary components reduces device complexity and power consumption while maintaining the ability to correct realignment error and improve spectral purity
Solution Approach 2:
The patent changes the operational parameters of the oscillator by using an integrate and subtract circuit that operates on voltage integration rather than traditional phase and frequency detection. This parameter change enables realignment error compensation with simpler circuitry, reducing both device complexity and power consumption while maintaining spectral purity
Data Source
AI summary
Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.