MDLL Sampler Calibration for Reference Spur Reduction
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Solution Overview
Problem
Multiplying delay-locked loops (MDLLs) in electronic devices suffer from reference spurs due to time offsets between reference and feedback signals, which degrade the quality of output signals and impact electronic communications and synchronous operations.
Innovation Solution
A sampler calibrator is introduced to adjust the impedance of sampler components in the MDLL's locked-loop feedforward path, aligning edges of the reference and VCO output signals to reduce time offsets and thereby minimize reference spurs, using a phase detector and digital-to-analog converter to generate a calibration signal based on phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a sampler is used in the locked-loop feedforward path of an MDLL, then the output signal frequency can be synthesized, but reference spurs are generated due to time offsets between reference and feedback signals
Solution Approach 1:
The patent applies preliminary action by performing sampler calibration before normal MDLL operation. The calibration process pre-adjusts the sampler delay using a calibration signal to eliminate time offsets that would otherwise cause reference spurs during actual operation. This advance preparation removes the harmful effect before it manifests in the output signal.
Solution Approach 2:
The patent implements feedback by using a feedback path that routes the VCO output signal through a divider back to the sampler. This feedback mechanism allows the system to monitor and adjust the sampler timing based on the actual phase relationship between reference and feedback signals, thereby minimizing reference spurs through continuous correction.
2Device complexity
If the sampler delay is not calibrated, then the circuit operation is simple, but the edges of reference and VCO output signals are misaligned causing time offsets
Solution Approach 1:
The patent applies self-service by implementing an automatic calibration mechanism that adjusts the sampler delay without requiring manual intervention. The calibration circuit generates a calibration signal, detects phase differences automatically, and adjusts the sampler timing autonomously. This self-calibrating feature maintains signal edge alignment while minimizing the need for external calibration procedures.
3Ease of manufacture
If sampler components impedance is fixed, then the device is easier to manufacture, but the time offset cannot be adjusted to minimize reference spurs
Solution Approach 1:
The patent applies dynamics by transforming the fixed impedance sampler components into adjustable impedance elements. The calibration circuit modifies the impedance of sampler components (such as resistors or capacitors) dynamically during the calibration process to adjust the sampler delay. This dynamic adjustment capability enables precise time offset correction while maintaining ease of manufacture through standardized adjustable components.
Data Source
AI summary
An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.