Multiple Data Rate Wiring Encoding for Chip Area Reduction
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Solution Overview
Problem
Integrated circuits require numerous wires for interconnecting components, which consume significant silicon or routing layer area and result in high power consumption due to signal toggling rates.
Innovation Solution
Implementing multiple data rate (MDR) wiring with encoding, replacing single data rate wires and using MDR conversion circuitry that includes driver, repeater, and receiver/decoder circuits, along with encoding to mitigate power consumption, and utilizing source synchronous bus and clock gating for efficient signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single data rate wires are used to interconnect components, then the wiring is simple to implement, but the silicon area and routing layer area consumed is substantial
Solution Approach 1:
The patent merges multiple single data rate wire functions into a single multiple data rate wire that can transmit multiple data streams simultaneously. By combining several data channels into one physical wire using time-division multiplexing and encoding techniques, the patent reduces the total number of wires needed while maintaining ease of implementation through standardized MDR interfaces and conversion circuitry.
2Area of stationary object
If multiple data rate wiring is implemented to reduce area, then the silicon area and routing layer area are reduced, but the device complexity increases due to MDR conversion circuitry
Solution Approach 1:
The patent introduces MDR conversion circuitry as an intermediary component that bridges single data rate interfaces and multiple data rate wiring. These conversion circuits act as mediators that encode data for transmission over MDR wires and decode received signals, enabling area reduction while managing complexity through modular, standardized interface components that can be reused throughout the system.
Solution Approach 2:
The patent segments the MDR conversion functionality into distinct modular components: encoding circuits at the transmitter end, MDR driver circuits, repeater circuits along the wire, and receiver/decoder circuits at the destination. This segmentation allows each component to be optimized independently and reused multiple times in the system, reducing overall complexity through modularity and standardization.
3Area of stationary object
If high data rate transmission is used to reduce wiring area, then the area is reduced, but the dynamic power consumption increases due to signal toggling rates
Solution Approach 1:
The patent employs periodic action through clock gating mechanisms that control when data transmission occurs on MDR wires. By enabling transmission only during necessary time periods and putting circuits into low-power states during idle periods, the patent reduces dynamic power consumption associated with continuous high-frequency signal toggling while maintaining high data rates when active.
Solution Approach 2:
The patent changes operational parameters dynamically by adjusting data transmission rates and clock frequencies based on actual data traffic requirements. The MDR conversion circuitry can modulate transmission parameters such as encoding schemes, clock gating enable/disable states, and data rate selections to optimize the balance between wiring area utilization and dynamic power consumption under different operating conditions.
Data Source
AI summary
A method and apparatus for using multiple data rate (MDR) wiring with encoding is described herein. Single data rate wires are replaced with MDR wires and signals are processed through MDR circuitry. The MDR circuitry may include MDR driver circuitry, MDR repeater circuitry and MDR receiver/decoder circuitry. An encoding circuit may be included in the MDR circuitry to mitigate power consumption due to signal toggling rates. The MDR circuitry may be implemented at multiple clock rates, and with source synchronous bus circuitry and clock gates.