Meander Line Resistor Structure for Memory Circuit Miniaturization
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and reducing the physical size of semiconductor chips while maintaining performance and reducing power consumption, particularly in memory circuits, where traditional resistor structures contribute to increased form factor and parasitic capacitance.
Innovation Solution
The implementation of a meander line resistor structure, comprising a series of resistors connected by doped regions or poly connectors, formed on top of active regions of a semiconductor device, which allows for compact design and adjustable resistance through switches, reducing parasitic capacitance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional resistor structures are used in memory circuits, then the circuit functionality is achieved, but the form factor increases and parasitic capacitance increases
Solution Approach 1:
The patent transforms the traditional planar resistor layout into a three-dimensional meander line structure that extends vertically across multiple interlayer dielectric layers. This dimensional transition allows the resistor to achieve compact horizontal footprint while maintaining sufficient resistance value, thereby reducing both form factor and parasitic capacitance simultaneously
Solution Approach 2:
The meander line resistor is nested within the existing semiconductor structure by integrating it through multiple interlayer dielectric layers and connecting to active regions. The resistor path winds through available spaces between other components, effectively utilizing vertical stacking to reduce horizontal area occupation
2Quantity of substance
If semiconductor process node is shrunk to improve integration density, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The resistor is segmented into multiple sections distributed across different interlayer dielectric layers, with each segment contributing to the total resistance. This segmentation allows the overall resistance value to be achieved through cumulative effect of smaller, more manufacturable segments, reducing the precision burden on any single feature
Solution Approach 2:
The patent changes the geometric parameters of the resistor structure by extending it vertically through multiple layers rather than horizontally in a single plane. This parameter transformation allows achieving high integration density without proportionally increasing manufacturing precision requirements at the sub-20 nm node
3Area of stationary object
If meander line resistor structure is implemented, then form factor is reduced and parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The meander line resistor structure serves multiple functions simultaneously: it provides the required resistance value, achieves compact form factor, reduces parasitic capacitance, and integrates with existing semiconductor processes. The same structural approach can be applied to different resistance values and circuit locations, making it a universal solution rather than a specialized complex structure
Solution Approach 2:
The patent merges the resistor structure with the existing interlayer dielectric layers and active regions of the semiconductor device. Rather than adding a separate complex structure, the resistor is combined with the existing fabrication layers, thereby reducing overall device complexity while achieving the desired form factor reduction
Data Source
AI summary
A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact.