Meandering Data Signal Path for Hold Time Control
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Solution Overview
Problem
The miniaturization of semiconductor integrated circuits leads to increased delay in clock signal lines, resulting in longer data hold times, particularly in fin type FETs, which cannot be effectively addressed by increasing the number of data buffers without expanding the circuit area.
Innovation Solution
Incorporating a delay line with gate wirings in the same layer as the gate electrodes of fin FETs in the data signal path from the data output node of the buffer to the input node of the flip-flop, allowing for control of data hold time without excessive circuit area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a plurality of data buffers are provided in series to adjust data signal delay, then the data hold time can be controlled, but the circuit area increases
Solution Approach 1:
The patent transitions from adjusting delay in the time dimension (using multiple data buffers in series) to adjusting delay in the spatial dimension (using a meandering data signal path). The data signal path is configured to extend in a meandering pattern through the substrate, utilizing physical path length to control signal propagation delay. This dimensional shift allows delay adjustment without adding multiple buffer stages, thereby reducing circuit area while maintaining controllable data hold time.
2Loss of time
If the number of data buffers is increased to compensate for increased clock signal delay, then the data hold time can be adjusted, but the circuit area expands
Solution Approach 1:
The meandering data signal path serves multiple functions simultaneously: it provides delay adjustment for data hold time control, occupies substrate area efficiently to accommodate other circuit elements, and maintains signal integrity without requiring additional buffer components. This multi-functional approach replaces the traditional method of using multiple data buffers, achieving delay control while reducing overall device complexity and circuit area.
Data Source
AI summary
Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.