Meandering Gate Oxide TFT Parasitic Current Reduction
Solution Overview
Problem
Oxide semiconductor thin film transistors (TFTs) face performance limitations due to parasitic currents between sources and drains when they have a high W/L ratio and are fabricated in limited areas, which hinders the enhancement of their performance even when using oxide semiconductor materials.
Innovation Solution
The design includes a gate with meandering patterns and an etching stop layer covering most of the substrate, with contact openings that allow the source and drain to be connected to the semiconductor layer without being in contact with each other, reducing parasitic currents and enhancing device performance. Additionally, capacitor electrode patterns are integrated to efficiently utilize layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the W/L ratio of channel width and channel length is increased to improve device performance, then carrier mobility and threshold voltage uniformity are enhanced, but parasitic currents occur between sources and drains which deteriorates device performance
Solution Approach 1:
The gate is divided into multiple gate electrodes arranged in a meandering pattern, which segments the channel into multiple sections. This segmentation allows for better control of the electric field distribution and reduces parasitic currents between sources and drains while maintaining a high effective W/L ratio for improved device performance
Solution Approach 2:
The gate structure transitions from a simple linear arrangement to a meandering two-dimensional pattern. This dimensional change allows the gate to achieve a high effective channel width while fitting within a limited layout area, and the meandering pattern specifically helps to reduce parasitic currents by creating isolation regions between adjacent gate segments
2Reliability
If the channel width and channel length are increased to achieve high W/L ratio, then device performance is improved, but the layout area required increases which conflicts with limited device region
Solution Approach 1:
The gate structure transitions from a simple linear arrangement to a meandering two-dimensional pattern. This dimensional change allows the gate to achieve a high effective channel width while fitting within a limited layout area, effectively resolving the contradiction between performance and area constraints
Solution Approach 2:
The meandering gate pattern uses curved and bent geometries instead of straight lines, allowing the channel to fold back on itself multiple times within a compact area. This curvature-based design achieves a long effective channel length and large effective width without proportionally increasing the bounding box area
3Reliability
If oxide semiconductor materials are used to fabricate channels, then carrier mobility is improved, but parasitic currents still occur which limits performance enhancement
Solution Approach 1:
The gate is segmented into multiple electrodes in a meandering pattern, which creates isolated regions that prevent parasitic current paths between sources and drains. This segmentation works in conjunction with oxide semiconductor channels to maintain high carrier mobility while eliminating the harmful parasitic effects
Solution Approach 2:
The meandering gate structure acts as an intermediary element that mediates between the oxide semiconductor channel and the source/drain regions. The gate's complex pattern creates electric field distribution that prevents direct parasitic current paths while the oxide semiconductor maintains its high mobility characteristics in the channel region
Data Source
AI summary
An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.