Meandering Word Line Layers for High-Integration Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As electronic products become miniaturized and multifunctional, there is a need for high-capacity semiconductor memory devices with increased integration, which poses challenges in maintaining electrical characteristics and data reliability due to complex operating circuits and wiring structures.
Innovation Solution
A semiconductor memory device design featuring a semiconductor substrate with meandering word line layers, insulating layers, and a channel structure with a gate dielectric layer, where the word line layers have varying thicknesses and a meandering shape, and bit lines extending horizontally, enhancing integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to provide high-capacity semiconductor memory devices, then storage capacity is improved, but electrical characteristics and data reliability deteriorate due to complex operating circuits and wiring structures
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical stacking of word line layers. Multiple word line layers are stacked in the vertical direction with insulating layers between them, allowing increased integration capacity while maintaining electrical performance by utilizing the vertical dimension rather than expanding lateral wiring complexity
Solution Approach 2:
The word line structure is divided into multiple separate word line layers (first word line layer, second word line layer, third word line layer) stacked vertically. Each layer can be independently controlled and optimized, allowing complex storage capacity requirements to be met while maintaining simple electrical characteristics within each individual layer
2Length of moving object
If the word line layers are made thinner to reduce device size, then miniaturization is achieved, but resistance increases and voltage drop occurs
Solution Approach 1:
Instead of increasing the lateral thickness of individual word lines (which would increase device footprint), the patent stacks multiple thin word line layers in the vertical direction. This distributes the conductive path across multiple layers, reducing resistance and voltage drop without compromising miniaturization in the lateral dimensions
Solution Approach 2:
Multiple thin word line layers are electrically combined through the stacked structure to form an effective word line system with reduced resistance. The insulating layers between them provide electrical isolation while the overall stacked structure achieves the desired electrical characteristics
3Quantity of substance
If more word line layers are added to increase integration, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent resolves complexity by organizing multiple word lines in the vertical dimension rather than creating complex lateral wiring patterns. Each word line layer has a simple meandering shape, and the stacking arrangement provides clear spatial separation and independent control, reducing overall device complexity while increasing integration capacity
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate; a plurality of word line layers on the semiconductor substrate, each word line layer of the plurality of word line layers including an insulating line and a word line; a plurality of insulating layers in spaces between the plurality of word line layers, the plurality of insulating layers being apart from each other in a vertical direction on the semiconductor substrate; a channel structure extending in the vertical direction on the semiconductor substrate, the channel structure including a channel region and a gate dielectric layer surrounding the channel region; and a bit line on the channel structure, the bit line extending in a first horizontal direction perpendicular to the vertical direction and being connected to the channel structure, wherein the word line of each word line layer of the plurality of word line layers has a meandering shape.