Multi-Stage Media Access Control for Solid-State Memory
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Solution Overview
Problem
Existing solid-state memory storage subsystems face challenges in efficiently managing access requests, maintaining drive coherency, and handling internal operations like garbage collection and wear leveling, often requiring complex address translation and synchronization mechanisms that can be resource-intensive.
Innovation Solution
A multi-stage media access control system that separates tasks into discrete stages and components, using a media access request object to share information and manage execution timing across different processors and threads, eliminating the need for synchronization mechanisms and improving concurrent use of memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex synchronization mechanisms are used to manage access requests and maintain drive coherency, then data integrity is maintained, but system overhead and resource consumption increase
Solution Approach 1:
The patent segments the access request management into distinct stages: request submission, arbitration, and execution. Each stage is handled by separate hardware components (submission queue, arbitration logic, execution engine), eliminating the need for complex software-based synchronization mechanisms while maintaining data integrity through structured phase separation.
Solution Approach 2:
The patent introduces an intermediary arbitration layer that sits between request submission and execution. This arbitration logic acts as a mediator that coordinates access requests from multiple sources (host commands, garbage collection, wear leveling) without requiring direct synchronization between these sources, thereby reducing overall system complexity while preserving data coherence.
2Stability of the object's composition
If address translation and mapping operations are performed centrally, then drive coherency is maintained, but processing time and resource usage increase
Solution Approach 1:
The patent implements preliminary address translation by pre-mapping logical addresses to physical locations during the request submission phase. The submission queue stores requests with pre-computed physical addresses, so that when requests reach the execution stage, no additional translation time is needed. This maintains drive coherency through centralized mapping while reducing processing time by performing translation in advance.
Solution Approach 2:
The patent introduces a temporal dimension to address translation by separating it into different time phases: logical-to-physical mapping is performed during request submission (first dimension), and physical address verification occurs during execution (second dimension). This multi-dimensional approach maintains coherency checks while distributing translation operations across time, reducing any single processing bottleneck.
3Productivity
If internal maintenance operations (garbage collection, wear leveling) are processed alongside host commands, then storage optimization is achieved, but access request handling complexity increases
Solution Approach 1:
The patent creates a universal request handling architecture where the same submission queue, arbitration logic, and execution engine process both host commands and internal maintenance operations (garbage collection, wear leveling). This unified multi-functional system achieves storage optimization through concurrent internal operations while managing complexity by applying the same processing pipeline to all request types, eliminating the need for separate specialized handlers.
4Productivity
If synchronization mechanisms are eliminated to reduce overhead, then system performance improves, but coordinating access between multiple processors becomes difficult
Solution Approach 1:
The patent segments the multi-processor access coordination into distinct operational phases (submission, arbitration, execution) with clearly defined data flow between stages. Each processor operates independently within its assigned phase without requiring synchronization with others, as the segmented architecture naturally isolates their operations. This eliminates synchronization overhead while maintaining coordination through structured phase separation.
Data Source
AI summary
Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution. In embodiments, the execution manager traverses a list of received requests for memory access and dispatches commands for execution. In embodiments, if a request is directed to memory units which have reached a threshold for outstanding requests, the request may be skipped so that other requests can be dispatched for memory units which have not yet reached the threshold.