Media Controller Data Modification Tracking for Memory Subsystems

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Solution Overview

Problem

Conventional memory sub-systems experience increased latency and power consumption due to unconditionally executing read-write cycles, even when data has not been modified, especially in hybrid memory/storage systems where the memory sub-system controller is unaware of data changes since the last write operation.

Innovation Solution

A media controller in the memory sub-system is configured with a data modification tracker to monitor data traffic and skip or execute write/read-write cycles based on observed data modification requests, marking data blocks as modified or unmodified to determine whether to perform a write cycle, thereby reducing unnecessary operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read-write cycles are unconditionally executed to ensure data consistency, then data reliability is improved, but latency and power consumption increase

Engineering Contradiction:
Improvedata consistencyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by setting a write pending bit in the cache before issuing the write command to non-volatile memory. This preliminary marking allows the system to later determine whether a read-write cycle is actually needed by checking if the bit is set, thereby avoiding unnecessary cycles and reducing latency while maintaining data consistency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by monitoring whether data has been modified in the cache since the last write operation. The write pending bit serves as a feedback mechanism that indicates whether a subsequent read operation will actually result in data needing to be written back to non-volatile memory, allowing the system to conditionally execute read-write cycles based on actual data changes.

Inventive Principle:
Principle #23Feedback

2Reliability

If read-write cycles are unconditionally executed to ensure data consistency, then data reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedata consistencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The system performs preliminary actions by setting a write pending bit in the cache before issuing the write command to non-volatile memory. This preliminary marking allows the system to later determine whether a read-write cycle is actually needed by checking if the bit is set, thereby avoiding unnecessary cycles and reducing power consumption while maintaining data consistency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by monitoring whether data has been modified in the cache since the last write operation. The write pending bit serves as a feedback mechanism that indicates whether a subsequent read operation will actually result in data needing to be written back to non-volatile memory, allowing the system to conditionally execute read-write cycles based on actual data changes, thus reducing unnecessary power consumption.

Inventive Principle:
Principle #23Feedback

3Loss of time

If the memory sub-system controller monitors data changes to avoid unnecessary write cycles, then latency and power consumption are reduced, but device complexity increases

Engineering Contradiction:
ImprovelatencyVSAvoidcontroller complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system segments the monitoring function by implementing it at the cache level rather than requiring full controller-level intervention. The write pending bit is set by the cache controller based on simple comparison of data blocks, dividing the complexity into manageable pieces and allowing the main controller to focus on higher-level operations while the cache handles the monitoring logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache controller performs self-service by autonomously monitoring data changes and setting the write pending bit without requiring continuous intervention from the main memory sub-system controller. This self-monitoring capability reduces the burden on the main controller and simplifies the overall system architecture while still achieving the goal of avoiding unnecessary read-write cycles.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10714176B2Read-write cycle execution based on history
Publication Date: 2020.07.14 MICRON TECHNOLOGY INC
  • US10714176B2 patent drawing
  • US10714176B2 patent drawing
  • US10714176B2 patent drawing

AI summary

Aspects of the present disclosure configure a media controller of a memory component to skip execution of a read-write cycle for specific data if the media controller has not observed at least one prior data modification request from a memory sub-system controller that causes modification of the specific data. For example, a media controller of a first memory component can be configured to include a data modification tracker to monitor a memory channel for data modification requests to a second memory component and to track data modification requests that have been observed by the media controller on the memory channel, where the memory channel may be one shared by the first and second memory components.