Media Controller for Transparent LRDIMM In-Memory Processing
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Solution Overview
Problem
Current In-Memory Processing (IMP) architectures face limitations due to the high cost and limited memory capacity of custom memory devices like JEDEC High-Bandwidth Memory (HBM) and Micron's Hybrid Memory Cube, which restrict their suitability for replacing commodity RAM in compute nodes, leading to fragmented memory usage and a limited scope of applications.
Innovation Solution
A media controller (MDC) is introduced to enable In-Memory Processing using standard commodity memory devices and protocols, allowing the IMP unit to access main memory by reassembling addresses and rescheduling requests, thereby increasing memory capacity and bandwidth while maintaining compatibility with traditional memory organizations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If custom memory devices like HBM or HMC are used for In-Memory Processing, then bandwidth and processing performance are improved, but cost increases and memory capacity is limited
Solution Approach 1:
The patent replaces expensive custom memory devices (HBM, HMC) with commodity DDR4 memory devices that are cheaper and more readily available. The system uses standard DDR4 devices with a memory controller that enables In-Memory Processing capabilities, effectively making expensive specialized hardware unnecessary by leveraging inexpensive commodity memory with software/firmware control.
2Productivity
If custom memory devices are used for In-Memory Processing, then processing performance is improved, but memory capacity is limited
Solution Approach 1:
The patent makes commodity DDR4 memory devices serve multiple functions: they act as both standard memory for the CPU and as In-Memory Processing acceleration. The memory controller enables the same physical memory to be used for both traditional computing and IMP operations, eliminating the need for separate specialized memory devices and thereby increasing available capacity for IMP.
Solution Approach 2:
The system dynamically switches between different operational modes of the memory device - it can operate as standard DDR4 memory for CPU access or as an In-Memory Processing device with enhanced capabilities. This dynamic reconfiguration allows the same hardware to adapt its function based on workload requirements, maximizing both performance and capacity utilization.
3Productivity
If IMP is tightly integrated with specialized memory, then bandwidth is improved, but adaptability to different memory types is reduced
Solution Approach 1:
The patent introduces a memory controller as an intermediary layer between the CPU and commodity DDR4 memory devices. This controller implements the protocol translation and control logic needed to enable In-Memory Processing over standard DDR4 interfaces, acting as a mediator that allows IMP to work with commodity memory without requiring tight integration with specialized memory devices.
4Ease of manufacture
If commodity memory is used for In-Memory Processing, then cost is reduced and capacity is increased, but integration complexity increases
Solution Approach 1:
The memory controller is integrated into the memory module itself (as in LRDIMM architecture), allowing the memory device to self-manage the complexity of enabling In-Memory Processing. The controller handles protocol translation, address mapping, and coordination with the CPU, freeing the system integrator from managing this complexity while still providing access to commodity memory with IMP capabilities.
Data Source
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AI summary
The invention provides a media controller for enabling in-memory computing with a main memory in a computing device. The MDC comprises an in-memory processor 109 configured to access the main memory 105 based on a first linear main memory address and to perform computations on data from the main memory 105. It further comprises a slave physical layer 111 configured to serve a request from a host 102 to access the main memory 105, wherein the request comprises a type of access and an address information. The MDC 108 also comprises a reverse memory controller (RMC) 110 configured to reassemble a second linear main memory address from a plurality of protocol fields contained in the address information, and to provide the second linear main memory address and the type of access to a local memory controller (LMC) 107. The LMC 107 is configured to grant the IMP 109 access to the main memory 105 and to reschedule the request from the host 102 to access the main memory 105, as long as computations and access to the main memory 105 performed by the IMP 109 are active and if the first and second linear memory addresses are both included in a predetermined address range.