Media Peripheral Interface Data Strobe Signal Edge Capture

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Solution Overview

Problem

Current communication protocols between processors and peripheral devices are inadequate for handling high-speed data transfer in complex electronic devices, requiring a more efficient and reliable method to manage clock signals and data transfer.

Innovation Solution

A media peripheral interface is introduced, featuring a clock port, data I/Os, and a data strobe port, which transfers clock signals and data strobe signals to capture command and data information, improving data reliability by utilizing rising and falling edges of the data strobe signal for data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a simple communication protocol is used between processor and peripheral device, then device complexity is reduced, but data transfer speed and reliability deteriorate

Engineering Contradiction:
Improvecommunication protocol complexityVSAvoiddata transfer speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The communication protocol is segmented into distinct phases: command phase for control signals and address phase for data transfer. This segmentation allows each phase to be optimized independently, maintaining protocol simplicity while enabling high-speed data transfer through dedicated data I/Os and strobe signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protocol dynamically switches between command mode and data mode based on the operation requirements. The media peripheral interface dynamically manages data I/Os and strobe signals to adapt to different transfer speeds and modes, allowing the system to achieve high-speed performance when needed while maintaining simplicity for control operations.

Inventive Principle:
Principle #15Dynamics

2Productivity

If high-speed data transfer is implemented, then productivity is improved, but data reliability deteriorates due to timing errors and signal integrity issues

Engineering Contradiction:
Improvedata transfer rateVSAvoiddata capture accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A data strobe signal is introduced as an intermediary between the data I/Os and the data capture process. The strobe signal acts as a synchronization mediator that coordinates the timing between data transmission and data latching, ensuring reliable data capture at high transfer rates by providing clear timing references for both transmitter and receiver.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protocol uses periodic clock signals and strobe signals to synchronize data transfer operations. These periodic signals provide regular timing references that ensure data is captured at optimal moments in the transmission cycle, maintaining reliability even at high transfer speeds by enforcing consistent timing intervals.

Inventive Principle:
Principle #19Periodic action

3Productivity

If data is captured on both rising and falling edges of strobe signal, then productivity is improved through double data rate transfer, but device complexity increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidinterface circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The protocol merges command transfer and data transfer into a unified interface structure with shared data I/Os. By combining these functions and using a single strobe signal that supports both rising and falling edge triggering, the system achieves double data rate transfer without proportionally increasing interface complexity, as the same physical resources handle multiple functions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9588543B2Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device
Publication Date: 2017.03.07 MEDIATEK INC
  • US9588543B2 patent drawing
  • US9588543B2 patent drawing
  • US9588543B2 patent drawing

AI summary

A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.