Media Processor Shared Memory Segmentation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Media-capable PC systems require high-speed memory access for both host CPU and media processors to synchronize quickly and meet strict frame timing constraints, especially in live video and audio processing, where existing memory systems often fail to provide rapid and uninterrupted access due to virtual memory schemes and pre-emptive scheduling.

Innovation Solution

Implementing a shared memory system with separate address translation tables for media processors, allowing them to maintain persistent address mappings even when the parent processor is swapped out, enabling concurrent memory access and reducing latency and buffering issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If virtual memory schemes and pre-emptive scheduling are used in existing memory systems, then system flexibility and resource management are improved, but memory access speed and continuity deteriorate, causing latency and buffering issues

Engineering Contradiction:

Improvesystem flexibilityVSAvoidmemory access speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the memory system into separate physical memory spaces for media processors, isolated from the host CPU's virtual memory management. This segmentation allows media processors to access dedicated physical memory directly without being subject to the host's virtual memory schemes, thereby maintaining high-speed continuous access while the host maintains its flexible virtual memory management independently.

Inventive Principle:

Principle #1Segmentation

2Productivity

If the parent processor is swapped out to run other tasks, then system productivity is improved, but media processor access to memory is interrupted, causing dropped frames and latency

Engineering Contradiction:

Improvesystem productivityVSAvoidmedia processing continuity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent creates separate address translation tables and physical memory spaces for media processors, independent of the host CPU's address space. This allows the media processors to maintain persistent access to their dedicated physical memory even when the host processor is swapped out or interrupted, ensuring uninterrupted media processing and preventing dropped frames while the host can freely switch between tasks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system pre-establishes separate address translation tables and physical memory allocations for media processors before the host processor needs to be swapped out. This preliminary setup ensures that media processors have their own persistent memory access paths already in place, eliminating the need for memory access interruption when host tasks need to be switched.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If shared memory access is implemented without separate address translation, then device complexity is reduced, but access latency increases due to swap overhead

Engineering Contradiction:

Improvememory system complexityVSAvoidmemory access latency

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent introduces separate address translation tables for media processors, segmenting the address translation function from the host CPU's unified virtual memory management. While this adds some complexity, it eliminates swap overhead by allowing media processors to directly access physical memory through their own translation tables, significantly reducing access latency and improving real-time performance.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8667249B2Systems and methods exchanging data between processors through concurrent shared memory

Publication Date: 2014.03.04 INTEL CORP

AI summary

A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.