Media Transmission System Reducing Output Delay via Offset Time Stamps
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Solution Overview
Problem
Existing media transmission systems face challenges in reducing output delays and avoiding video quality degradation due to phase fluctuations in SDI signals during IP transmission.
Innovation Solution
A media transmission system comprising a transmitting device that receives and packetizes video signals, applies time stamps based on SMPTE_EPOCH alignment points, and transmits these packets as IP signals. The receiving device depacketizes the IP signals, applies an offset to the time stamps, and outputs the video signals without waiting for the next alignment point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the receiver waits for the next alignment point to output the video signal, then the output timing is synchronized to SMPTE_EPOCH, but the output delay increases by nearly one frame
Solution Approach 1:
The transmitter pre-calculates and embeds the alignment point timing information into time stamps within each RTP packet during packetization. The receiver uses these pre-prepared time stamps to determine output timing without waiting for the next alignment point, thus reducing delay while maintaining synchronization.
Solution Approach 2:
Time stamps serve as an intermediary carrier that conveys alignment point timing information from the transmitter to the receiver. This intermediary mechanism allows the receiver to calculate precise output timing based on embedded reference points rather than waiting for actual alignment point arrivals.
2Measurement precision
If the time stamp is set to the input time of the SDI signal frame, then the timing reflects actual signal arrival, but phase fluctuations from jitter cause video quality degradation
Solution Approach 1:
The invention extracts the alignment point timing information from the actual variable-time SDI signal input and separates it from the packetization process. By using fixed SMPTE_EPOCH-based alignment points as time stamp references instead of actual signal input times, the system removes the harmful effect of jitter while preserving accurate timing structure.
Solution Approach 2:
The time stamp parameter is changed from reflecting actual variable input timing (which includes jitter) to reflecting fixed SMPTE_EPOCH alignment point timing. This parameter transformation converts the time stamp from a jitter-containing measurement to a stable reference that ensures consistent video output quality.
3Reliability
If the receiver outputs video frames at alignment point timing, then synchronization is maintained, but the system complexity increases due to frame-based timing control
Solution Approach 1:
The timing control is segmented into two independent functions: the transmitter segment handles alignment point detection and time stamp embedding, while the receiver segment handles time stamp reading and output timing calculation. This segmentation distributes complexity across both ends rather than concentrating it in the receiver's frame-based control logic.
Data Source
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AI summary
A media transmission system includes a media transmitting device (1) including: a video signal reception circuit (111) that receives a video signal generated in association with the timing of an alignment point, a packetization circuit (112) that converts the video signal into a plurality of packets in frames, a time stamping circuit (113) that applies a time stamp corresponding to the timing of the alignment point at the time of generation to each packet; and an IP signal transmission circuit (114) that transmits each packet as an IP signal; and the media receiving device (2) including: an IP signal reception circuit (211) that receives the packet, a depacketization circuit (212) that reproduces a frame of the video signal from the packet, an offset control circuit (213) that outputs the reproduced frame at an output timing obtained by adding an offset to the alignment point of the time stamp; and a video signal transmission circuit (214) that outputs the frame output from the offset control circuit (213).