Medium-Fine TDC Calibration for Sub-Gate Phase Alignment
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Solution Overview
Problem
All Digital Phase Locked Loops (ADPLLs) face performance limitations due to the finite resolution of Time to Digital Converters (TDCs), which introduce quantization errors and affect the in-band noise and spurious tone at the PLL output, particularly in applications requiring stringent phase noise performance like radar systems.
Innovation Solution
The implementation of a Medium-Fine based TDC topology with a calibration method that utilizes a combination of medium and fine resolution delay units, including delay inverters, D flip-flops, and a decoder, to minimize misalignment caused by component mismatch and routing issues, achieving sub-gate resolution and precise phase alignment through incremental delay calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC with finite resolution is used in ADPLL, then the device complexity is reduced, but quantization errors increase affecting phase noise performance
Solution Approach 1:
The TDC is divided into multiple delay units with different resolution levels (medium resolution and fine resolution). Each delay unit contains multiple delay elements that can be selectively activated. The fine resolution delay unit provides sub-gate resolution measurements while the medium resolution unit handles coarser measurements, together achieving high precision phase measurement without requiring a single complex high-resolution TDC structure
Solution Approach 2:
The TDC structure dynamically switches between medium resolution and fine resolution delay units based on the required measurement precision. The calibration process dynamically adjusts the delay element settings to achieve optimal phase alignment. This dynamic operation allows the system to adapt resolution requirements while maintaining manageable device complexity
2Measurement precision
If medium and fine resolution delay units are combined, then quantization errors are reduced, but device complexity increases
Solution Approach 1:
The time measurement range is segmented into two resolution levels: medium resolution for broader time intervals and fine resolution for smaller time intervals. The medium resolution delay unit covers larger time spans with coarser granularity, while the fine resolution delay unit covers smaller time spans with sub-gate granularity. This segmentation allows high precision measurement across the full time range without requiring an excessively complex single-unit structure
Solution Approach 2:
The fine resolution delay unit is nested within the overall TDC structure, with its output combined with the medium resolution delay unit output. The fine resolution unit provides detailed measurements that complement the broader measurements from the medium resolution unit, creating a nested measurement hierarchy that achieves high precision while managing complexity through modular organization
3Measurement precision
If calibration is performed to achieve sub-gate resolution, then phase alignment precision is improved, but the time required for calibration increases
Solution Approach 1:
The calibration process performs preliminary alignment of the medium and fine resolution delay units before normal operation. During calibration, the delay elements are pre-adjusted to achieve optimal phase alignment between different signal paths. This preliminary action ensures that when the TDC operates in normal mode, the delay units are already synchronized, enabling sub-gate resolution measurements without requiring continuous calibration
Solution Approach 2:
The calibration process uses feedback from the phase detector to iteratively adjust the delay element settings. The output of the TDC is fed back to the calibration logic, which adjusts the delay unit configurations to minimize phase error. This feedback mechanism automates the calibration process, reducing manual intervention time while achieving precise phase alignment between medium and fine resolution paths
Data Source
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AI summary
Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.