Medium-Voltage Transistor Structure for Low-Threshold Level Shifters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Level shifter circuits face challenges in operating medium voltage transistors due to high threshold voltage requirements, which can lead to increased current leakage and power consumption, especially when trying to interface with low voltage transistors.
Innovation Solution
Incorporating a p-well region and an n-type lightly-doped source/drain (NLDD) region in medium voltage transistors, along with a buffer layer over the NLDD region, to reduce threshold voltage and minimize current leakage while enabling operation by low voltage transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the gate oxide layer is made thick to support medium voltages, then the transistor can handle medium voltage operation, but the threshold voltage becomes too high to be operated by low voltage transistors
Solution Approach 1:
The patent applies local quality by creating a lightly-doped source/drain region with different doping concentration than the heavily-doped extension regions. This localized variation in dopant concentration allows the channel to have reduced threshold voltage in specific areas, enabling low-voltage operation while maintaining overall medium-voltage capability through the thick gate oxide layer.
Solution Approach 2:
The patent changes the dopant concentration parameter by introducing a lightly-doped source/drain region with lower dopant concentration compared to conventional fully-heavy-doped structures. This parameter change reduces the threshold voltage to enable operation by low-voltage transistors while the thick gate oxide maintains medium-voltage handling capability.
2Ease of operation
If the dopant concentration in the source/drain region is reduced to lower threshold voltage, then the transistor can be operated by low voltage transistors, but current leakage increases
Solution Approach 1:
The patent segments the source/drain structure into distinct regions: lightly-doped source/drain regions for threshold voltage control and heavily-doped extension regions for current leakage suppression. This segmentation allows each region to perform its specific function optimally - the lightly-doped regions enable low-voltage operation while the heavily-doped extension regions maintain low off-state current.
Solution Approach 2:
The patent applies local quality by creating spatially varying dopant concentrations within the source/drain structure. The lightly-doped regions are positioned where threshold voltage control is needed, while heavily-doped extension regions are positioned where current leakage suppression is critical, allowing simultaneous optimization of both parameters.
3Temperature
If medium voltage transistors are used in level shifter circuits, then higher voltage levels can be achieved, but power consumption increases
Solution Approach 1:
The patent changes the dopant concentration parameter to create a lightly-doped source/drain region, which reduces the threshold voltage of medium-voltage transistors. This parameter change allows the transistors to switch at lower voltages, reducing the energy required for switching operations while maintaining the ability to handle medium voltage levels during signal transmission.
Data Source
AI summary
A medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. Moreover, the medium voltage transistor may include an n-type lightly-doped source/drain (NLDD) region in which an N+ source/drain region of the medium voltage transistor is included. The light doping in the NLDD region enables a threshold voltage (Vi) to be reduced while enabling medium voltage operation at the N+ source/drain region. To reduce the amount of current leakage in the medium voltage transistor due to the light doping in the NLDD region, a buffer layer may be included over and/or on a portion of the NLDD region under a gate structure of the medium voltage transistor. The NLDD region and the thermal region of the medium voltage transistor enables the threshold voltage of the medium voltage transistor while maintaining the same current leakage performance or reducing current leakage in the medium voltage transistor.