MeFET-MTJ Memory Gate Using VCMA to Protect Tunnel Barriers
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Solution Overview
Problem
Conventional magneto-resistive random-access memory (MRAM) cells, such as STT-MRAM and SOT-MRAM, face challenges with tunnel barrier reliability degradation and high power consumption due to the write current passing through the thin tunnel barrier layer, which affects their performance and efficiency.
Innovation Solution
The integration of a magneto-electric field effect transistor (MeFET) with a magnetic tunnel junction (MTJ) within its gate structure, utilizing voltage-controlled magnetic anisotropy (VCMA) to switch the magnetization state between anti-parallel and parallel states without passing current through the tunnel barrier layer, thereby improving tunnel barrier reliability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write current is passed through the tunnel barrier layer in conventional MRAM cells, then magnetization state switching is achieved, but tunnel barrier reliability degrades and power consumption increases
Solution Approach 1:
The patent replaces the conventional current-driven magnetization switching mechanism with a voltage-controlled mechanism. Instead of passing write current through the tunnel barrier layer to switch magnetization states, the invention applies voltage to the gate electrode to induce magnetic anisotropy changes via the VCMA effect. This substitution eliminates direct current flow through the tunnel barrier, thereby improving reliability and reducing power consumption while achieving the same magnetization switching function.
Solution Approach 2:
The gate electrode serves as an intermediary component that enables indirect control of the magnetization state. Rather than directly passing current through the tunnel barrier layer, the gate electrode mediates the switching process by applying voltage that induces VCMA effects in the adjacent ferromagnetic layer. This intermediary mechanism allows magnetization switching without the harmful direct current path, resolving the contradiction between switching capability and barrier integrity.
2Length of moving object
If thin tunnel barrier layer is used in MRAM cells, then device size is reduced and integration is improved, but tunnel barrier reliability degrades due to write current stress
Solution Approach 1:
The invention replaces the current-driven switching mechanism with voltage-controlled VCMA switching, eliminating the need for thick tunnel barriers that could withstand high write currents. By using voltage applied to the gate electrode to induce magnetic anisotropy changes, the system can use thinner tunnel barriers without compromising reliability, as no direct write current passes through the barrier to cause degradation.
Solution Approach 2:
The invention changes the control parameter from current to voltage. Instead of relying on current flow through the tunnel barrier to switch states, the system uses voltage applied to the gate electrode to control magnetization switching via VCMA. This parameter change enables the use of thinner tunnel barriers while maintaining reliability, as voltage control does not subject the thin barrier to the same degradation mechanisms as current-driven approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MeFET-based memory device achieves improved tunnel barrier reliability and reduced power consumption by switching between capacitance states using VCMA, enabling efficient data storage with enhanced reliability and lower energy usage compared to traditional MRAM devices.
Implementation Method 1
utilizing voltage-controlled magnetic anisotropy (VCMA) to switch the magnetization state between anti-parallel and parallel states
Implementation Method 2
Conventional magneto-resistive random-access memory (MRAM) cells
Data Source
AI summary
A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.