Melt-Annealed Source-Drain Regions for Lower FinFET Contact Resistance
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Solution Overview
Problem
The existing methods for forming source and drain regions in FinFETs result in high contact resistance due to the planar interface between the silicide regions and the source/drain regions, which limits the performance of integrated circuits.
Innovation Solution
The use of a melt anneal process that molten portions of the source and drain regions, allowing for a curved interface with the overlying silicide regions, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planar interface is formed between silicide regions and source/drain regions through conventional epitaxy, then the manufacturing process is simple, but contact resistance is high
Solution Approach 1:
The patent applies curvature by forming a non-planar, curved interface between the silicide regions and source/drain regions through selective removal of dielectric material. This curved interface increases the contact area between silicide and semiconductor, thereby reducing contact resistance compared to conventional planar interfaces.
Solution Approach 2:
The patent applies local quality by creating regions of different dielectric thickness around the source/drain regions. The dielectric layer is selectively removed in specific areas to expose the source/drain regions, forming localized curved interfaces where silicide contact is needed, while maintaining dielectric coverage in other areas.
2Reliability
If dopants are activated through conventional annealing, then diffusion is minimized, but dopant activation is insufficient
Solution Approach 1:
The patent applies phase transitions by utilizing the melting and solidification of the source/drain regions during rapid thermal annealing. This phase transition enables super activation of dopants as the molten state facilitates rapid dopant redistribution, while the quick solidification minimizes unwanted diffusion and maintains sharp junction profiles.
Solution Approach 2:
The patent applies parameter changes by rapidly changing the temperature parameters during annealing - heating to a temperature that melts the source/drain regions for dopant activation, then quickly cooling to solidify and freeze the dopant distribution. This dynamic parameter control achieves both high activation and minimal diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The melt anneal process effectively reduces contact resistance and enhances the performance of FinFETs by achieving super activation of dopants and minimizing diffusion in non-molten regions, improving short-channel effects and Drain Induced Barrier Lowering (DIBL) performance.
Implementation Method 1
The use of a melt anneal process that molten portions of the source and drain regions
Implementation Method 2
allowing for a curved interface with the overlying silicide regions, thereby reducing contact resistance
Data Source
AI summary
A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.