Membrane Potential Holding Circuits for Low-Power Spiking Networks
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Solution Overview
Problem
Conventional artificial intelligence technologies require large amounts of power for learning operations, making them difficult to execute in edge devices, while spiking neural networks implemented on semiconductor chips face challenges with capacitor and resistor integration due to limitations in CMOS technology, hindering efficient data processing.
Innovation Solution
A neural network device utilizing synapse and neuron circuits with secondary battery elements and resistive elements to mimic brain-like information processing, incorporating synapse circuits with synaptic weights and neuron circuits that generate spike signals, and a reset control circuit to manage membrane potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional AI technologies are used for learning operations, then computation capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent replaces conventional digital computing systems with biological neural network-inspired systems. Specifically, it uses membrane potential-based computation where neurons integrate synaptic inputs through capacitor charging, eliminating the need for extensive numerical computations required by conventional AI learning operations, thereby significantly reducing power consumption while maintaining learning capability
Solution Approach 2:
The patent changes the fundamental computation parameter from digital bits to continuous membrane potentials. By using analog voltage signals to represent neural states and employing biological plausibility constraints (such as refractory periods and threshold firing), the system achieves efficient learning operations with reduced computational overhead and lower power requirements
2Ease of operation
If spiking neural networks are implemented on semiconductor chips using conventional capacitors and resistors, then brain-like processing is achieved, but integration is hindered by CMOS technology limitations
Solution Approach 1:
The patent introduces a novel intermediate component called the 'membrane potential holding circuit' that mediates between synaptic input and neuron output. This circuit uses a capacitor connected in series with a current source, where the capacitor voltage represents the membrane potential. This intermediary structure enables brain-like processing by naturally implementing integration and thresholding functions while being compatible with CMOS fabrication processes
Solution Approach 2:
The patent changes the physical implementation parameters by using transistor-based circuits to emulate biological components. Instead of conventional passive capacitors and resistors that are difficult to integrate at scale, the system uses active transistor circuits that can be more easily fabricated in CMOS technology, while still achieving the desired membrane potential dynamics through careful control of time constants and threshold voltages
3Speed
If neuron circuits use large capacitor capacity and high resistance values to fire at low frequency, then spiking behavior is achieved, but device area increases
Solution Approach 1:
The patent introduces dynamic control mechanisms including voltage-dependent ion channels and adaptive refractory periods. These dynamic elements allow the neuron to adjust its time constant and firing characteristics in real-time based on input strength and historical activity, enabling low-frequency spiking behavior with smaller, more compact circuit areas compared to static resistor-capacitor implementations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The neural network device achieves efficient data processing by mimicking brain operations with a reduced power consumption, enabling appropriate integration and operation of spiking neural networks on semiconductor chips.
Implementation Method 1
a secondary battery element configured to accumulate a charge according to the synaptic current supplied to the first terminal
Implementation Method 2
a resistive element configured to leak the charges accumulated in the secondary battery element
Data Source
AI summary
A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit includes a first terminal to which a synaptic current is supplied. The first neuron circuit includes a secondary battery element, a spike generation circuit, and a reset control circuit. The secondary battery element accumulates a charge according to the synaptic current supplied to the first terminal. The spike generation circuit generates a spike signal when the membrane potential generated from the secondary battery element is larger than a threshold potential being a predetermined potential. The reset control circuit releases the charge accumulated in the secondary battery element during a refractory period being a predetermined time after generation of the spike signal.