Memory Access Connection Circuit for 32-Bit to 64-Bit Address Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Certain electronic devices, such as 32-bit peripherals or direct memory access circuits, are limited in their ability to address the entire memory space of 64-bit processors, leading to inaccessible address ranges.
Innovation Solution
A connection circuit that receives input addresses, compares them with a threshold, and generates additional address bits to extend the addressable range, allowing 32-bit circuits to access memory areas beyond their direct capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 32-bit peripheral circuit is used, then the device complexity is reduced, but the addressable memory space is limited to 4 Gigabytes
Solution Approach 1:
The patent introduces a connection circuit as an intermediary component between the 32-bit peripheral circuit and the memory space. This connection circuit translates 32-bit addresses into 64-bit addresses, enabling the peripheral circuit to access memory beyond its native 4GB limit without modifying the peripheral circuit itself. The connection circuit acts as a mediator that resolves the address width mismatch.
Solution Approach 2:
The patent extends the address space by adding additional address bits (most significant bits) to the 32-bit address, transforming it into a 64-bit address. This dimensional expansion allows the system to access memory locations beyond the original 32-bit addressable range, effectively moving from a 4GB addressable space to a much larger space while keeping the peripheral circuit simple.
2Area of stationary object
If the addressable memory space is extended beyond 4 Gigabytes, then the memory capacity is increased, but the peripheral circuit cannot access the extended address range
Solution Approach 1:
The connection circuit serves as a mediator that translates addresses between the peripheral circuit's native address space and the extended memory space. It receives addresses from the peripheral circuit, compares them with a threshold address, and generates appropriate output addresses that map to the extended memory range, thereby enabling access to previously inaccessible memory areas.
Solution Approach 2:
The patent changes the address parameter by dynamically generating additional most significant bits based on the input address and a threshold comparison. When the input address is below the threshold, the connection circuit generates specific high-order bits to map the address to the extended memory range, effectively transforming the address parameter to enable access to larger memory spaces.
3Area of stationary object
If additional address bits are generated by the connection circuit, then the output address range is extended, but the circuit requires comparison logic
Solution Approach 1:
The connection circuit segments the address translation process into distinct functional parts: an address comparison unit that compares the input address with a threshold, and an address generation unit that creates the output address based on the comparison result. This segmentation allows for modular implementation and simplifies the overall design by breaking down the complex address translation task into manageable components.
Data Source
AI summary
A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.