Memory Access Bypass for Instruction Misses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems with hierarchical memory, the translation of virtual memory addresses to physical addresses across multiple memory levels can significantly impact performance due to memory access misses, which are not efficiently managed by existing systems.
Innovation Solution
A code patcher mechanism that maintains a count of memory misses for instructions and, when a threshold is exceeded, allows direct access to memory devices like flash memory, bypassing the operating system, thereby reducing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If virtual memory mapping is used to provide a single addressing scheme for applications, then ease of operation is improved, but memory access performance deteriorates due to translation overhead and memory misses
Solution Approach 1:
The patent applies dynamics by making the memory access path changeable based on conditions. Instructions can dynamically switch between going through the virtual memory mapping system (for normal operation) or bypassing it directly to memory devices (for performance-critical paths). This is achieved by maintaining a count of memory misses per instruction and modifying instructions based on whether the threshold is exceeded, allowing the system to adapt its memory access behavior dynamically.
Solution Approach 2:
The patent segments the memory access path into two distinct routes: the conventional virtual memory mapping path and a direct memory access path. By segmenting this way, the system can route different instructions through different paths based on their memory access patterns, allowing high-performance direct access for instructions with frequent misses while maintaining virtual memory protection for others.
2Speed
If direct memory access is granted to bypass the operating system, then memory access speed is improved, but system control and security deteriorate
Solution Approach 1:
The patent implements feedback by monitoring memory miss counts for each instruction and using this information to determine whether to modify the instruction's memory access path. The system continuously tracks performance metrics and adjusts behavior accordingly, only granting direct access when data shows persistent misses exceeding a threshold, thus ensuring direct access is granted only when performance benefits outweigh control risks.
Solution Approach 2:
The patent applies local quality by treating different instructions differently based on their individual memory access characteristics. Rather than applying a uniform policy to all instructions, the system analyzes and modifies only those specific instructions that exhibit problematic memory access patterns, leaving other instructions unchanged and maintaining normal system control for them.
3Productivity
If memory access threshold is set low, then application performance is improved by more direct access, but system overhead increases due to more frequent modifications
Solution Approach 1:
The patent changes the parameter of memory access behavior based on the threshold condition. By adjusting the threshold parameter, the system can control the balance between performance improvement and overhead. A higher threshold reduces the frequency of modifications and system overhead, while a lower threshold maximizes performance benefits by granting direct access more readily.
Data Source
AI summary
A non-transitory computer-readable storage medium may include instructions stored thereon. When executed by at least one processor, the instructions may be configured to cause a computing system to at least maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application, and grant the instruction direct access to memory, bypassing an operating system running on the computer, based on the count of memory misses meeting or exceeding a threshold.