Memory Access Category Task Dispatch for Multi-Core Cache Latency
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Solution Overview
Problem
In multi-core processing systems, cache pollution occurs due to tasks accessing different memory address ranges, leading to increased latency as data is constantly removed and replaced in shared core caches, affecting performance.
Innovation Solution
Assigning tasks to processor cores based on memory access categories, where tasks accessing the same memory address range are dispatched to the same core, and cache hostile tasks are segregated to dedicated cores, reducing cache latency by minimizing data replacement in shared caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tasks are assigned to shared processor cores, then resource utilization is improved, but cache pollution increases leading to higher latency
Solution Approach 1:
The patent segments tasks into different categories based on their memory access patterns (e.g., read-heavy, write-heavy, random access, sequential access). Tasks are then assigned to specific processor cores based on these categories, creating dedicated execution domains that reduce cache pollution while maintaining high resource utilization through efficient task distribution.
2Productivity
If tasks accessing different memory address ranges share the same core, then core utilization is improved, but cache replacement frequency increases
Solution Approach 1:
The patent applies local quality by assigning different memory access categories to different processor cores. Each core is dedicated to handling specific access patterns (e.g., one core for sequential access, another for random access), ensuring that each core maintains consistent cache access patterns and avoids the harmful effect of frequent cache replacement that occurs when mixed access patterns share the same core.
3Adaptability or versatility
If cache is frequently updated to accommodate different memory access patterns, then adaptability is improved, but performance deteriorates due to increased latency
Solution Approach 1:
The patent introduces dynamic task categorization and assignment mechanisms that analyze memory access patterns in real-time. Tasks are dynamically classified into appropriate categories and assigned to suitable cores based on their access characteristics, allowing the system to adapt to varying workloads while maintaining optimal cache performance and minimizing latency through intelligent, dynamic resource allocation.
Data Source
AI summary
Provided are a computer program product, system, and method for determining memory access categories to use to assign tasks to processor cores to execute. A computer system has a plurality of cores, each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. At task is processed to determine one of the cores on which to dispatch the task. A memory access category of a plurality of memory access categories is determined to which the processed task is assigned. The processed task is dispatched to the core assigned the determined memory access category.