Multi-Plane Memory Access Controller Channel Segmentation
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Solution Overview
Problem
Current semiconductor memory systems lack efficient control over access operations across multiple memory devices with multi-plane arrays, leading to suboptimal performance and increased power consumption.
Innovation Solution
A semiconductor memory system with a host controller, access controller, read buffer, and write buffer that manages access operations across multiple planes by prioritizing channels, ways, and planes, allowing for rapid and efficient data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If access operations are performed on multiple memory devices without controlled ordering, then data storage capacity is increased, but access efficiency and performance deteriorate
Solution Approach 1:
The patent segments the multi-plane array into multiple channels, with each channel containing multiple planes across multiple memory devices. The access controller independently manages each channel, dividing the complex control task into smaller, manageable units. This segmentation enables parallel access to different channels while maintaining simplified control logic for each channel, thereby improving access efficiency without proportionally increasing control complexity.
Solution Approach 2:
The access controller performs preliminary actions by pre-establishing channel priorities and plane selection criteria before actual access operations. The controller determines the access sequence in advance based on channel priorities, ensuring that when multiple access requests arrive, the controller can immediately execute according to the pre-determined sequence without complex real-time decision-making, thus improving access efficiency while keeping control complexity manageable.
2Speed
If multiple planes are accessed simultaneously without priority control, then data transfer speed is increased, but power consumption increases
Solution Approach 1:
The patent implements dynamic plane selection within each channel based on priority levels. The access controller dynamically determines which plane to access next by evaluating channel priorities and current access states, rather than using a fixed access pattern. This dynamic approach allows the system to optimize data transfer speed by accessing high-priority planes while avoiding unnecessary accesses to low-priority planes, thereby reducing power consumption while maintaining high transfer speeds when needed.
Solution Approach 2:
The system changes access parameters (channel priority levels, plane selection criteria) based on operational conditions. By adjusting which channels and planes are prioritized for access, the system can optimize between speed and power consumption depending on the specific access pattern requirements, allowing rapid data transfer when priority channels are accessed while conserving power when such transfers are not required.
3Quantity of substance
If access operations are performed on all planes of all memory devices, then storage capacity is fully utilized, but access time increases
Solution Approach 1:
By segmenting the multi-plane array into multiple independent channels with hierarchical organization (channels containing planes containing memory devices), the system can utilize full storage capacity across all devices while maintaining fast access times. The segmentation allows parallel access to multiple channels simultaneously, so that not all planes need to be accessed sequentially - only the necessary planes within prioritized channels are accessed first, reducing access time while still providing access to the entire storage capacity when needed.
Solution Approach 2:
The access controller performs preliminary actions by pre-establishing access priorities for different channels and planes before actual data access operations. This preliminary organization allows the system to quickly access high-priority planes that contain frequently accessed data, reducing average access time, while the hierarchical structure ensures that less frequently accessed planes in lower-priority channels are still accessible, maintaining full storage capacity utilization.
Data Source
AI summary
A semiconductor memory system may include a plurality of memory devices each configured to have multiple planes, and an access controller configured to access each of the multiple planes corresponding to each of the plurality of memory devices as a unit memory.