Memory Access Collar Bypasses Processor for Fast Testing
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Solution Overview
Problem
Existing memory test systems require processor involvement for accessing and testing memory, which is slow, complex, and inconvenient, especially during development, test, and manufacture, as they rely on the processor to read and write memory locations.
Innovation Solution
A memory access system that includes a test collar logic block to bypass the processor, allowing direct access to memory via a test bus, enabling fast and independent memory access and initialization without processor involvement, using auto-address increment for efficient data transfer during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor is used to access memory for testing, then the memory can be accessed, but the access speed is slow and the operation is complicated
Solution Approach 1:
The patent extracts the memory access function from the processor by introducing a dedicated test collar interface. This separate interface allows memory to be accessed directly for testing purposes without involving the processor, thereby improving access speed and simplifying operations during test modes.
Solution Approach 2:
The test collar acts as an intermediary between the test equipment and memory. It provides a dedicated pathway for memory access during testing, bypassing the processor entirely. This mediator enables fast, direct memory access while keeping the processor available for its normal functions.
2Ease of operation
If the processor is involved in memory access, then memory can be read and written, but the processor must be operational which limits convenience during development and testing
Solution Approach 1:
The patent segments the memory access pathway into two independent channels: one through the processor for normal operation, and another through the test collar for testing and development. This segmentation allows memory to be accessed conveniently during development and testing without requiring the processor to be operational, while maintaining full processor functionality during normal operation.
3Productivity
If traditional memory access methods are used, then the system can operate, but testing time is excessive and thorough testing within limited timeframe is not possible
Solution Approach 1:
The test collar enables self-service memory access where testing equipment can directly read and write memory without processor intervention. This autonomous access path dramatically reduces testing time and allows thorough testing within limited timeframes by eliminating the processor as a bottleneck.
Data Source
AI summary
A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.