Memory Access Control Using Address Aliasing and Markers
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Solution Overview
Problem
Current memory access control systems, relying on MPUs or MMUs, incur high costs in logic gates, power consumption, and have poor granularity, particularly due to the need for address comparators and coarse segmentation.
Innovation Solution
Implementing a memory access control system that assigns each memory location to alias address zones with markers, allowing fine-grained access control without the need for MPUs or MMUs, using an address decoder and verification circuit to manage access based on operating modes and alias addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MPUs or MMUs are used for memory access control, then access control functionality is provided, but logic gate cost increases (over 10k gates)
Solution Approach 1:
The patent extracts the address verification function from the complex MPU/MMU architecture and implements it directly in the memory device using a marker stored at each memory location. This marker contains the verified address information, allowing the memory device itself to perform access control without requiring external comparators or protection units, thereby reducing logic gate cost while maintaining access control functionality.
Solution Approach 2:
The patent uses a marker that is a copy of the verified address information stored at each memory location. This marker serves as a simplified representation of the access control rules, replacing the need for complex address comparison logic. The marker can be read and verified to determine whether access is permitted, providing a lightweight alternative to full MPU/MMU functionality.
2Reliability
If address comparators are added to verify memory access, then access control is achieved, but power consumption increases
Solution Approach 1:
The patent removes the need for continuous address comparison operations by pre-storing the verified address information in a marker at each memory location. During access, the system only needs to read and verify this pre-computed marker rather than performing complex real-time address comparisons, significantly reducing power consumption while maintaining verification reliability.
3Adaptability or versatility
If memory segments are defined with traditional granularity (32 bytes to 4 KB), then access control zones are established, but fine-grained control is lost
Solution Approach 1:
The patent segments the memory space into alias address zones, where each zone is associated with a specific marker. This segmentation approach allows for fine-grained control at the level of individual alias zones rather than requiring fixed-size segments. Each memory location can have its own marker with verified address information, enabling precise control over which specific addresses are accessible, thereby achieving fine-grained control without being constrained by traditional segment sizes.
Data Source
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AI summary
The present disclosure concerns a memory access control system comprising: a processing device (302) capable of operating in a plurality of operating modes, and of accessing a memory (200) using a plurality of address aliases; and a verification circuit (312) configured: to receive, in relation with a first read operation of a first memory location in the memory (200), an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.