Memory Access Control Device for Consecutive Data
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Solution Overview
Problem
Existing memory access methods decrease efficiency when increasing bus width, as they unnecessarily access data other than the desired data, leading to inefficient access of laterally or longitudinally consecutive data.
Innovation Solution
A memory access control device and method that divides data into different memory areas based on predetermined bits of an access address, allowing simultaneous access to these areas in the same clock cycle, reducing unnecessary data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bus width is increased to broaden access bandwidth, then the amount of data accessed at a time increases, but the access efficiency decreases due to unnecessary data being accessed simultaneously
Solution Approach 1:
The patent divides the memory into multiple banks (first bank and second bank) and further segments data within each bank into different regions (first region, second region, third region). This segmentation allows selective access to specific data regions in specific banks, preventing unnecessary data from being accessed simultaneously and maintaining high access efficiency even with increased bus width.
2Ease of operation
If data are accessed in lateral direction, then laterally consecutive data can be retrieved, but longitudinally consecutive data access becomes inefficient due to unnecessary data access
Solution Approach 1:
The patent segments memory into multiple banks and further divides data within each bank into different regions. This hierarchical segmentation enables the system to selectively access only the required data regions in the appropriate banks, whether lateral or longitudinal access is needed, thereby maintaining efficiency for both access directions.
Solution Approach 2:
The patent introduces a bank dimension in addition to the traditional linear memory address space. By organizing data across multiple banks with different region assignments, the system can access longitudinally consecutive data efficiently by selecting appropriate banks, effectively adding a dimensional approach to solve the directional access efficiency problem.
3Ease of operation
If data are accessed in longitudinal direction, then longitudinally consecutive data can be retrieved, but laterally consecutive data access becomes inefficient due to unnecessary data access
Solution Approach 1:
The patent segments memory into multiple banks and further divides data within each bank into different regions. This hierarchical segmentation enables the system to selectively access only the required data regions in the appropriate banks, whether lateral or longitudinal access is needed, thereby maintaining efficiency for both access directions.
Solution Approach 2:
The patent introduces a bank dimension in addition to the traditional linear memory address space. By organizing data across multiple banks with different region assignments, the system can access laterally consecutive data efficiently by selecting appropriate banks, effectively adding a dimensional approach to solve the directional access efficiency problem.
4Speed
If memory frequency is increased to broaden access bandwidth, then the access speed increases, but the frequency cannot exceed the maximum supported by the memory
Solution Approach 1:
The patent merges multiple memory banks (first bank and second bank) into a unified memory system that can be accessed simultaneously. By combining the capacity and access paths of multiple banks, the system achieves increased effective bandwidth and access speed without requiring higher clock frequencies, thus respecting the maximum frequency support while still achieving high performance.
Data Source
AI summary
An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.