Memory Access Control Device for Cache Hit Ratio Optimization

Solution Overview

Problem

Conventional systems face reduced cache line array capacity for I/O devices when both arithmetic and I/O devices access main memory simultaneously, leading to decreased transfer speed and increased power consumption due to lower cache hit ratios and frequent main memory access.

Innovation Solution

A memory access control device that manages access between main memory and cache memory using a history buffer unit and cache tag unit to prioritize write access and balance read/write access, employing counters to optimize cache usage and reduce main memory access frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single cache memory is shared between arithmetic device and I/O device, then device complexity is reduced, but cache hit ratio decreases when both access simultaneously

Engineering Contradiction:

Improvecache memory structureVSAvoidcache hit ratio

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The cache memory is segmented into a first cache line array dedicated to the arithmetic device and a second cache line array dedicated to the I/O device. The tag array is also segmented into a first tag array for the arithmetic device and a second tag array for the I/O device. This segmentation allows each device type to have dedicated cache resources, preventing interference and maintaining high cache hit ratios for both arithmetic and I/O operations simultaneously.

Inventive Principle:

Principle #1Segmentation

2Speed

If cache line array capacity is reduced for I/O device access, then access speed for arithmetic device is improved, but transfer speed for I/O data decreases

Engineering Contradiction:

Improvearithmetic device access speedVSAvoidI/O data transfer speed

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The cache memory is segmented into a first cache line array dedicated to the arithmetic device and a second cache line array dedicated to the I/O device. The tag array is also segmented into a first tag array for the arithmetic device and a second tag array for the I/O device. This segmentation allows each device type to have dedicated cache resources, preventing interference and maintaining high cache hit ratios for both arithmetic and I/O operations simultaneously.

Inventive Principle:

Principle #1Segmentation

3Speed

If cache line array capacity is reduced for I/O device access, then access speed for arithmetic device is improved, but power consumption increases

Engineering Contradiction:

Improvearithmetic device access speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The cache memory is segmented into a first cache line array dedicated to the arithmetic device and a second cache line array dedicated to the I/O device. The tag array is also segmented into a first tag array for the arithmetic device and a second tag array for the I/O device. This segmentation allows each device type to have dedicated cache resources, preventing interference and maintaining high cache hit ratios for both arithmetic and I/O operations simultaneously.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9684602B2Memory access control device, cache memory and semiconductor device

Publication Date: 2017.06.20 KK TOSHIBA

AI summary

A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.