Memory Access Control Circuit for Blending Processing
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Solution Overview
Problem
Existing memory access control systems in graphic drawing apparatuses face inefficiencies in blending processing due to delays and state transitions during image data read and write operations, leading to increased processing time and resource utilization.
Innovation Solution
A memory access control circuit with an address transmitting unit, data receiving unit, backup units, and a data delay circuit that manages state transitions and data processing to minimize delays, allowing for efficient read and write operations by storing and restoring register values during state changes and utilizing a data delay circuit to synchronize data processing with state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If state transitions are performed during memory read/write operations in blending processing, then different image data can be processed sequentially, but processing time is increased due to delays during state transitions
Solution Approach 1:
The patent applies preliminary action by performing data writing to the memory in advance during periods when data reading is not required. Specifically, the system writes output image data to the memory during the period between reading the current output image and reading the previous output image, thereby preparing data ahead of time and eliminating waiting delays during state transitions.
Solution Approach 2:
The patent implements continuity of useful action by ensuring that the memory access control circuit continuously performs either reading or writing operations without idle periods. The control circuit is designed to overlap read and write operations in time, so that while one operation is occurring, another is prepared or executed, eliminating the processing time losses that would occur with sequential state transitions.
2Device complexity
If data is read and written sequentially during blending processing, then memory access control is simplified, but resource utilization is reduced due to idle periods
Solution Approach 1:
The patent applies dynamics by making the memory access control circuit adaptive and flexible in its operation. The control circuit dynamically adjusts its behavior based on the current state and timing requirements, switching between different access patterns as needed. This dynamic control allows the system to optimize resource utilization without requiring a complex fixed architecture.
Solution Approach 2:
The control circuit performs preliminary actions by anticipating future data needs and preparing data in advance. It writes output image data to the memory before it is needed for subsequent processing, and reads data ahead of when it is required for blending operations. This lookahead approach improves resource utilization while keeping the control logic relatively simple.
3Reliability
If delay circuits are used to synchronize data with state transitions, then data timing is synchronized, but device complexity increases
Solution Approach 1:
The patent merges the delay circuit functionality with the existing state transition logic and control signals. Instead of adding separate delay circuits, the system integrates timing adjustments into the control circuit's state machine, using the same control signals to coordinate both state transitions and data timing. This integration achieves synchronization without significantly increasing device complexity.
Solution Approach 2:
The control circuit performs self-service by using its own internal timing and state information to automatically synchronize data operations. The circuit monitors its own state transitions and adjusts data read/write timing based on its internal clock and state signals, eliminating the need for external delay circuits or complex synchronization mechanisms.
Data Source
AI summary
A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.