Memory Access Controller Dynamic Page Management

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Solution Overview

Problem

Processor-based systems using dynamic memory face increased memory access times due to the need to close and reopen memory pages, which impacts CPU performance and bandwidth, especially when accessing non-contiguous memory locations within the same memory bank.

Innovation Solution

A memory access controller that configures each memory bank individually to either keep or close memory pages after access, based on the type of data stored, optimizing access times by predicting future access patterns or dynamically adjusting the configuration during runtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory pages are kept open after access to improve contiguous access speed, then memory access time is reduced for contiguous accesses, but memory access time increases for non-contiguous accesses due to required page closing

Engineering Contradiction:
Improvememory access timeVSAvoidadaptability to different access patterns
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic memory page management by monitoring access patterns and automatically adjusting page open/close behavior. The system transitions from static page management to dynamic adaptation based on whether accesses are contiguous or non-contiguous, resolving the contradiction between optimizing for contiguous accesses while maintaining flexibility for non-contiguous accesses.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs feedback mechanisms by monitoring memory access patterns and using this information to make intelligent decisions about page management. The controller observes access sequences and adjusts page open/close operations accordingly, enabling the system to adapt to different access patterns and optimize performance for both contiguous and non-contiguous accesses.

Inventive Principle:
Principle #23Feedback

2Device complexity

If a single memory page configuration is used for all memory banks, then device complexity is reduced, but memory access time increases for banks with different access patterns

Engineering Contradiction:
Improvememory controller configurationVSAvoidmemory access time
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent applies local quality by allowing each memory bank to have independent page open configuration bits, enabling different banks to be optimized for their specific access patterns. This per-bank customization resolves the contradiction between maintaining simple unified configuration and achieving optimized performance for diverse access patterns across different banks.

Inventive Principle:
Principle #3Local quality

3Speed

If memory pages are closed after each access to ensure memory bank readiness for new pages, then memory access time is reduced for non-contiguous accesses, but memory access time increases for contiguous accesses due to unnecessary page closing and reopening

Engineering Contradiction:
Improvememory access timeVSAvoidtime lost in page closing operations
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system performs preliminary monitoring of access patterns before making page management decisions. By anticipating whether the next access will be to the same page or a different page, the system can proactively maintain pages open when beneficial, avoiding unnecessary close/open operations and eliminating wasted time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from monitored access patterns to intelligently decide whether to close or maintain pages open. This feedback-driven approach prevents unnecessary page closing for contiguous accesses while ensuring pages are closed when non-contiguous accesses are detected, optimizing the balance between page open maintenance and memory bank readiness.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2409235B1Memory access controller, systems, and methods for optimizing memory access times
Publication Date: 2019.01.09 QUALCOMM INC
  • EP2409235B1 patent drawingFigure 1
  • EP2409235B1 patent drawingFigure 2
  • EP2409235B1 patent drawingFigure 3

AI summary

A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.