Memory Access Controller Dynamic Request Issuance
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Solution Overview
Problem
In shared-memory-type processors with multiple cores, direct memory connection is limited by transistor density and wiring constraints, leading to network congestion and increased memory latency, which degrades system performance, especially in High Performance Computing (HPC) environments.
Innovation Solution
A memory access control device that calculates an in-process number of load requests and replies within a predetermined period, adjusts issuance limits based on these metrics, and outputs hold instructions to prevent network congestion by dynamically managing the number of requests to the memory network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple cores directly connect to memory, then memory access performance is improved, but transistor density and wiring constraints are exceeded
Solution Approach 1:
The patent introduces a memory access control device as an intermediary between processor cores and memory. This controller dynamically manages memory access requests from multiple cores, preventing network congestion while maintaining high access performance. The controller acts as a mediator that balances the competing demands of multiple cores without requiring direct connections from all cores to memory.
2Device complexity
If cores indirectly connect to memory via network, then transistor density constraints are satisfied, but network congestion occurs and memory latency increases
Solution Approach 1:
The memory access control device implements feedback mechanisms to monitor network load conditions and dynamically adjust memory access request issuance. By detecting congestion states and responding with appropriate control actions, the system prevents latency increases while maintaining feasible device complexity through indirect connections.
Solution Approach 2:
The patent employs dynamic control of memory access requests based on real-time network conditions. The controller adapts its behavior according to current load status, varying the number of permitted requests to optimize performance while avoiding congestion. This dynamic approach allows the system to maintain low latency despite using indirect network connections.
3Speed
If cores unconditionally issue memory requests, then processing speed is maintained, but network congestion and performance degradation occur
Solution Approach 1:
The memory access control device implements partial action by dynamically limiting the number of memory access requests permitted from processor cores. Instead of allowing unconditional request issuance, the controller selectively permits a controlled number of requests based on current network load, preventing congestion while maintaining adequate processing throughput.
Data Source
AI summary
A memory access control device includes: an in-process number calculating unit that calculates an in-process number, which is a number of in-process load requests, at a predetermined time to a memory network; a reply number calculating unit that calculates a number of replies of the load requests received in a predetermined period from the predetermined time; an issuance number limitation unit that calculates an issuance limit value of the load requests in the predetermined period; an update determination unit that decides the issuance limit value regarding a next period on a base of the in-process number, the number of replies, and the issuance limit value in the predetermined period; and a hold determination unit that outputs a hold instruction of the load requests to a request pipeline connected to the memory network when the in-process number is larger than the issuance limit value regarding the next period.