Memory Access Controller for Conflict-Free Data Output
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Solution Overview
Problem
In arithmetic processing devices, the varying data read sizes of memory access requests can lead to conflicts and delays in data output, resulting in deteriorated processing performance due to misalignment in the issuance and output orders of memory access requests and responses.
Innovation Solution
A memory access controller that coordinates memory access by outputting read commands at conflict-avoiding timings, using buffers to store and manage data output based on an output start timing, and delaying subsequent data outputs to maintain the correct reception order of memory access requests, thereby ensuring data is output in the intended order and preventing collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access requests with different data read sizes are processed sequentially without coordination, then the memory can be accessed continuously, but data output conflicts and order misalignment occur
Solution Approach 1:
The memory access controller determines the data read size of each memory access request in advance and coordinates the output timing of read commands accordingly. By performing this preliminary sizing and timing coordination, the system ensures that data is output in the correct order while maintaining continuous memory access throughput.
2Speed
If subsequent memory access requests are processed immediately without delay control, then processing speed is improved, but output collisions and data order errors occur
Solution Approach 1:
The system dynamically adjusts the output timing of subsequent memory access requests based on the data read size of preceding requests. When a subsequent request would cause an output collision, its output timing is delayed appropriately. This dynamic timing adjustment maintains high processing speed while preventing output collisions and data order errors.
Data Source
AI summary
A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.