Memory Access Controller Shift Register Parallelism
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Solution Overview
Problem
The existing memory access controllers require multiple shift registers to manage varying degrees of parallelism in memory access, leading to increased circuit complexity and unnecessary components when operating frequency is low.
Innovation Solution
A memory access controller with a request holding pipeline that uses a single series of shift registers to manage different degrees of parallelism by dynamically adjusting the shift signal timing based on the operation mode, resource number, and average request interval, allowing for flexible output of access commands to the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple shift registers are used to manage varying degrees of parallelism in memory access, then the memory access controller can operate at high frequencies with multiple banks in parallel, but the circuit scale and complexity increase
Solution Approach 1:
A single shift register is designed to perform multiple functions by dynamically changing its operation mode. The shift register can operate in different parallelism modes (e.g., 1-way, 2-way, 4-way parallel) by adjusting the shift timing and control signals, eliminating the need for multiple dedicated shift registers for different parallelism levels. This multi-functional design resolves the contradiction by providing high-memory access throughput across different operating frequencies without proportionally increasing circuit scale.
Solution Approach 2:
The shift register incorporates dynamic control mechanisms that allow it to adapt its operation based on the current operating frequency and required degree of parallelism. By dynamically adjusting shift clock timing, enable signals, and data latching behavior, the single shift register can optimize its performance for different memory access patterns and frequencies, maintaining high productivity without the static overhead of multiple fixed-function registers.
2Speed
If shift registers are designed for maximum operating frequency with maximum parallels, then high-throughput memory access is achieved at high frequencies, but unnecessary shift registers remain inactive at low operating frequencies
Solution Approach 1:
The single shift register is designed to universally handle all required parallelism levels by changing its operational configuration. At maximum operating frequency, it operates in high-parallelism mode to achieve maximum throughput. At lower frequencies, the same shift register transitions to lower-parallelism modes, dynamically adapting to the reduced processing capacity requirements. This eliminates the need to provision shift registers for maximum parallelism that would remain inactive at lower frequencies.
Solution Approach 2:
The shift register's operational parameters (shift clock frequency, data latching timing, enable signal duration) are dynamically changed based on the target operating frequency and desired parallelism level. By adjusting these parameters, the single shift register can efficiently operate across the full frequency range without requiring additional hardware resources, thus reducing the quantity of shift registers needed while maintaining optimal performance at each operating point.
3Ease of operation
If the shift register shifts data at fixed timing, then simple control logic is used, but the output timing of access commands cannot be flexibly adjusted for different memory access patterns
Solution Approach 1:
The shift register incorporates dynamic timing control that allows adjustment of data shift timing and output enable timing based on the required memory access pattern. Control signals such as shift enable, output enable, and clock timing can be dynamically adjusted to match different memory access requirements (e.g., sequential access, interleaved access, burst access). This dynamic control provides timing flexibility while maintaining relatively simple control logic through standardized control signal interfaces.
Solution Approach 2:
The shift register allows changing of timing parameters (shift clock phase, data latching point, output enable timing) to adapt to different memory access patterns. By modifying these temporal parameters rather than the fundamental shift operation, the system achieves versatile output timing flexibility while keeping the core control logic simple and reusable across different operating conditions.
Data Source
AI summary
An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.