Memory Access Controller Speculative Read Latency
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Solution Overview
Problem
In nonvolatile memory modules that combine volatile and nonvolatile memory, the latency increases when a cache miss occurs in the DRAM, leading to out-of-order data transmission, which prolongs the read latency compared to DRAM alone.
Innovation Solution
An arithmetic processing device with a memory access controller that issues speculative reads when the requested address is in the cache and normal reads when it's not, allowing for efficient data acquisition by managing cache hits and misses between DRAM and NAND type flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a nonvolatile memory module uses a DRAM cache with large capacity, then the storage capacity is improved, but the read latency increases when cache misses occur
Solution Approach 1:
The memory access controller performs preliminary actions by issuing speculative read commands to the DRAM cache before the host actually needs the data. By predicting which data will be accessed and pre-fetching it, the system prepares data in advance, reducing the latency impact when cache misses would otherwise occur and eliminating the need for handshaking protocols during actual data retrieval.
2Reliability
If a nonvolatile memory module uses normal read protocol with handshakes, then data transmission reliability is improved, but the read latency increases
Solution Approach 1:
The system skips the traditional handshake protocol by using speculative read commands that do not require handshaking between the host and memory module. The memory access controller directly issues read commands to the DRAM cache based on predicted access patterns, rushing through the data retrieval process without waiting for confirmation signals, thereby significantly reducing read latency while maintaining data integrity through alternative error handling mechanisms.
3Loss of time
If a nonvolatile memory module uses speculative read without handshakes, then the read latency is reduced, but the data may be acquired out of order
Solution Approach 1:
The memory access controller implements feedback mechanisms to track the status of speculative read operations and the order in which data is retrieved from the DRAM cache. By monitoring completion status and original request order, the controller can manage and reorder data transmission to maintain the correct sequence, ensuring that data is delivered to the host in the proper order despite the asynchronous nature of speculative reads.
Data Source
AI summary
An arithmetic processing device includes an arithmetic circuit and a memory access controller performing access control for a read request on a memory module including a volatile memory and a nonvolatile memory, the volatile memory operating as a cache of the nonvolatile memory. The memory access controller stores an address table on which unit addresses including a request address of the read request are registered, issues a speculative read to the memory module in response to the read request and update the address table when the request address is included in the unit addresses in the address table, and issues a normal read when the request address is not included in any of the unit addresses. When the normal read is issued, read data is received after transmitting a transmission request signal. When the speculative read is issued, read data are acquired when receiving a hit flag.