Memory Access Scheduling for Delay-Sensitive Multi-Channel Devices

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Solution Overview

Problem

Existing memory controllers struggle to instantaneously optimize performance for devices sensitive to delay time, and multi-channel memory systems incur high costs due to complex traffic control mechanisms.

Innovation Solution

A memory control system that divides devices into sets based on performance-delay relations, using front-end circuitries, traffic control circuitry, and back-end circuitries to adjust task schedules and optimize access requests according to device sensitivities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If decision tree with software/firmware updates is used to adjust access scheduling, then stability and predictability are improved, but instantaneous optimization capability for delay-sensitive devices deteriorates

Engineering Contradiction:

ImprovestabilityVSAvoidinstantaneous optimization capability

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent segments devices into multiple sets based on their sensitivity to access delay time. Different sets of devices are assigned to different front-end circuitries, allowing independent optimization strategies for each segment. This segmentation enables instantaneous optimization for delay-sensitive devices while maintaining stable scheduling for other devices, resolving the contradiction between stability and instantaneous optimization capability.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If complex traffic control mechanisms are employed to support multi-port and multi-channel applications, then device compatibility and functionality are improved, but system cost deteriorates

Engineering Contradiction:

Improvemulti-port and multi-channel supportVSAvoidsystem cost

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the memory control system into multiple independent front-end circuitries, each handling specific sets of devices. This segmentation allows the system to support multiple ports and channels without requiring a single complex traffic control mechanism, thereby reducing overall system cost while maintaining multi-port and multi-channel functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each front-end circuitry is designed to handle multiple types of access requests (read, write, etc.) and can serve different sets of devices. This multi-functionality allows the system to support various device types and configurations without requiring additional specialized control mechanisms, reducing system complexity and cost while maintaining versatility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12547311B2Memory control system and memory control method

Publication Date: 2026.02.10 REALTEK SEMICON CORP

AI summary

A memory control system includes front-end circuitries, a traffic control circuitry, and back-end circuitries. Each of the front-end circuitries is configured to receive access requests from a corresponding device in devices, and sequentially output the access requests to be a corresponding one of first requests. The traffic control circuitry is configured to output the first requests to be second requests. The back-end circuitries are configured to adjust a task schedule of a memory according to the second requests, in which performances of the devices have different sensitivities to an access delay time of the memory.