Memory Access Engine for Parallel Execution During Memory Latency
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Solution Overview
Problem
Memory access latency in computer processors severely degrades performance due to high-latency memory access tasks, particularly in systems using DRAM, leading to delays in processing other instructions and inefficient use of computing resources.
Innovation Solution
A memory access engine is introduced to execute memory access instructions independently, allowing the processor to continue executing other instructions without waiting for memory operations to complete, with status updates ensuring data dependencies are resolved before proceeding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the computer processor executes memory access instructions directly, then the memory access tasks are completed with basic processor resources, but the processing of other instructions is delayed and overall performance degrades
Solution Approach 1:
The patent divides the processor into two separate execution units: a first execution unit for executing memory access instructions and a second execution unit for executing other instructions. This segmentation allows memory access tasks to be handled independently by the first execution unit, preventing them from blocking the second execution unit and thereby reducing the loss of time for overall processor performance.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the first and second execution units. The buffer stores results from the first execution unit and provides status indications to the second execution unit, enabling the second execution unit to proceed with instructions that do not depend on memory access completion while maintaining data dependency correctness.
2Productivity
If the processor waits for memory access tasks to complete before processing other instructions, then data dependency is ensured, but computing resources are underutilized
Solution Approach 1:
The first execution unit provides status indications to the second execution unit regarding the completion status of memory access tasks. This feedback mechanism allows the second execution unit to determine whether it can safely proceed with instructions that may depend on memory access results, ensuring data dependency correctness while maximizing resource utilization by not unnecessarily waiting.
Solution Approach 2:
The patent implements dynamic instruction execution where the second execution unit adaptively determines whether to wait for memory access completion based on data dependency analysis. Instructions that do not depend on memory access results are executed immediately, while dependent instructions are delayed until the buffer indicates completion, thereby dynamically optimizing both reliability and productivity.
Data Source
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Figure 2A
AI summary
A computer system is presented. The computer system comprises a memory system that stores data, a computer processor, and a memory access engine. The memory access engine is configured to: receive a first instruction of a computing process from the computer processor, wherein the first instruction is for accessing the data from the memory system; acquire at least a part of the data from the memory system based on the first instruction; and after the acquisition of the at least a first part of the data, transmit an indication to the computer processor to enable the computer processor to execute a second instruction of the computing process.