Memory Access Reconstruction for End-to-End Integrity Checks
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Solution Overview
Problem
Current Systems on a Chip (SoCs) face challenges in meeting higher safety standards like ASIL D due to increased physical area consumption and timing issues from existing fault detection methods, which do not provide end-to-end coverage for memory access integrity.
Innovation Solution
Implementing an access reconstruction controller, comparator, and data integrity monitor that utilize feedback signals from memory to reconstruct and compare access and control information, enabling efficient detection of faults across memory interconnects, thereby reducing physical area consumption and improving operational frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing fault detection methods are implemented in SoCs, then fault detection capability is improved, but physical area consumption increases and timing issues occur
Solution Approach 1:
The patent implements feedback mechanisms where memory controllers send access information to monitors, which then provide fault detection results back to the system. This feedback loop enables comprehensive fault detection while optimizing resource usage by only monitoring when necessary, thus improving reliability without excessive area consumption
Solution Approach 2:
The fault detection system is segmented into separate functional blocks: memory controllers, monitors, and analysis units. This segmentation allows each component to perform its specific function efficiently, reducing overall area consumption while maintaining comprehensive fault detection capability across the memory interconnect
2Reliability
If existing fault detection methods are implemented in SoCs, then fault detection capability is improved, but timing issues occur
Solution Approach 1:
The system performs preliminary actions by capturing and storing access information at the memory controller before potential faults occur. Monitors then analyze this pre-captured data, allowing fault detection without adding critical path delays to the memory access operation itself
Solution Approach 2:
An intermediary monitoring structure is introduced that sits between the memory controller and the rest of the system. This intermediary captures access information and performs fault analysis in parallel, preventing timing issues by not blocking the main memory access path while still providing comprehensive fault detection
3Reliability
If end-to-end memory access integrity is achieved, then safety standards compliance is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality, serving both as the primary memory interface and as a source of access information for fault monitoring. This universality reduces overall device complexity by eliminating the need for separate dedicated monitoring hardware while still achieving end-to-end memory access integrity
Solution Approach 2:
The patent merges the fault monitoring functionality with the existing memory controller structure. By combining these functions, the system achieves comprehensive memory access integrity verification without the complexity overhead of completely separate monitoring systems, as the memory controller itself provides the access information needed for monitoring
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.