Variable Resistance Memory Access Latency Reduction
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Solution Overview
Problem
Variable resistance memory devices face challenges in reducing access latency due to differing access times for memory cells and other components sharing virtual address space, which affects the timing of read or write commands.
Innovation Solution
A nonvolatile memory device with an I/O circuit that receives and decodes packet signals in sequence to initiate and control core access operations, allowing part of the core access to begin before decoding the second packet signal, thereby reducing access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the memory device waits to receive all packet signals before initiating core access operation, then the timing control is simplified, but the access latency increases
Solution Approach 1:
The read circuit performs preliminary actions by initiating part of the core access operation in response to the first packet signal before the second packet signal is decoded. This allows the memory device to start processing earlier, reducing access latency without requiring complete signal reception before operation initiation.
Solution Approach 2:
The core access operation is segmented into multiple phases that can be executed independently. The read circuit handles the first phase in response to the first packet signal, while the I/O circuit continues to decode the second packet signal. This segmentation allows parallel processing and reduces overall access latency.
2Loss of time
If part of the core access operation is performed before all packet signals are received, then access latency is reduced, but the risk of operation interruption increases
Solution Approach 1:
The I/O circuit dynamically controls the core access operation by selectively continuing or discontinuing it based on the decoding result of the second packet signal. This dynamic adjustment allows the system to optimize between speed and reliability, completing the operation early when possible or interrupting when necessary.
Solution Approach 2:
The system uses feedback from the second packet signal decoding to control the continuation of the core access operation. The I/O circuit monitors the decoded information and provides feedback control, deciding whether to continue or discontinue the operation initiated by the read circuit, thereby ensuring operational reliability.
3Device complexity
If the I/O circuit decodes packet signals sequentially, then the decoding logic is simplified, but the overall access speed is reduced
Solution Approach 1:
The read circuit performs preliminary decoding and action in response to the first packet signal while the I/O circuit continues to decode the second packet signal. This preliminary action allows the system to process information in parallel, maintaining simplified decoding logic while improving access speed.
Data Source
AI summary
A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.