Memory Array Access Line Layout for Uniform Multi-Deck Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of memory devices with multiple decks results in varying electrical resistances due to differences in access line dimensions across decks, leading to increased power consumption and non-uniform signal transmission.
Innovation Solution
The implementation of dedicated processing steps for forming access lines, where a metallization layer is deposited and etched in one direction to form word lines, and then another layer is deposited and etched in a second direction to form digit lines, ensuring more uniform thickness and dimensions across decks, thereby reducing parasitic resistances and improving signal delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning steps are used to form access lines in memory devices with multiple decks, then the manufacturing process is simpler, but the access line dimensions vary across decks resulting in non-uniform electrical resistances
Solution Approach 1:
The patent divides the access line formation process into separate stages for different decks. First conductive lines are formed in a first deck, then second conductive lines are formed in a second deck using a different etching direction. This segmentation allows each deck's access lines to be optimized independently, achieving uniform dimensions and electrical resistances across multiple decks while managing complexity through systematic process division.
2Productivity
If access lines have varying dimensions across decks, then the manufacturing process is faster, but electrical resistances become non-uniform leading to increased power consumption
Solution Approach 1:
The patent changes the etching parameters between decks - specifically using different etching directions (first direction for first deck, second direction for second deck). This parameter change ensures that access lines in different decks achieve similar dimensions and electrical resistances, reducing power consumption variations across decks while maintaining efficient manufacturing through standardized process steps.
3Ease of manufacture
If conventional etching processes are used for all decks, then the process is more efficient, but access lines experience different etch rates resulting in tapered profiles and varying areas
Solution Approach 1:
The patent applies local quality by tailoring the etching direction to each specific deck. First conductive lines in the first deck are etched in a first direction, while second conductive lines in the second deck are etched in a second direction. This localized approach compensates for different etch rates experienced by access lines at different decks, ensuring uniform areas and eliminating tapered profiles while maintaining overall process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in better signal delivery and cell performance across multiple decks by ensuring access lines have similar dimensions, reducing exposure to contaminants, and providing more uniform thickness, which in turn reduces power consumption and enhances signal transmission uniformity.
Implementation Method 1
a metallization layer is deposited and etched in one direction to form word lines, and then another layer is deposited and etched in a second direction to form digit lines
Data Source
AI summary
Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.