Memory Access Line Voltage Control via Floating State
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Solution Overview
Problem
As memory cell density increases in memory devices like flash memory, controlling operations becomes challenging due to the complexity of managing access lines and voltages required for read, write, and erase operations, leading to inefficiencies in power consumption and operation time.
Innovation Solution
The implementation of a voltage generator and access line voltage controller that apply specific voltages to access lines during memory operations, including placing selected lines in a floating state to reduce power consumption and shorten programming time by utilizing coupling capacitances from adjacent lines to generate required voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density increases to improve storage capacity, then storage capacity is improved, but controlling operations becomes more difficult and power consumption increases
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing multiple memory cell strings. This segmentation allows independent control of different blocks, simplifying the control logic for high-density memory operations while maintaining high storage capacity.
Solution Approach 2:
The patent implements dynamic voltage control where select lines are placed in a floating state (high-impedance state) during certain operation phases. This dynamic switching between active and floating states reduces power consumption and simplifies control complexity by eliminating the need to actively drive all lines simultaneously.
2Reliability
If traditional voltage control methods are used during write operations, then data can be stored, but power consumption is high and programming time is long
Solution Approach 1:
The write operation is divided into distinct time phases: a first time period where select lines are actively driven to apply voltages for programming, and a second time period where select lines are placed in a floating state. This periodic switching reduces power consumption while ensuring reliable data storage during the active programming phase.
Solution Approach 2:
The patent utilizes coupling capacitances between adjacent memory cell strings to maintain voltages on select lines during the floating state. This self-service mechanism allows the system to maintain necessary voltage levels without active driving, significantly reducing power consumption while preserving programming integrity.
3Productivity
If all select lines are actively driven during write operations, then programming can be performed, but power consumption increases and operation time extends
Solution Approach 1:
The patent dynamically switches select lines between active driving state and floating state. During the active programming phase, selected select lines are driven to appropriate voltages. During subsequent phases, these lines are placed in a floating state, reducing power consumption without extending programming time because the critical programming operation completes during the active phase.
Solution Approach 2:
The patent introduces a floating state as an intermediary condition for select lines. This intermediate state allows lines to maintain voltage levels through coupling capacitances without active driving, bridging the gap between active programming and power-saving modes, thereby reducing overall power consumption while maintaining programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of memory operations by reducing power consumption and shortening the time needed to program memory cells, while maintaining accurate data storage and retrieval.
Implementation Method 1
utilizing coupling capacitances from adjacent lines to generate required voltages
Data Source
AI summary
Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described.